LM3S317 Luminary Micro, Inc, LM3S317 Datasheet - Page 166
![no-image](/images/no-image-200.jpg)
LM3S317
Manufacturer Part Number
LM3S317
Description
Lm3s317 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S317.pdf
(376 pages)
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General-Purpose Timers
166
Reset
Reset
Type
Type
Bit/Field
31:16
15:0
GPTM TimerA Interval Load (GPTMTAILR)
Offset 0x028
1/0 = 1 if timer is configured in 32-bit mode; 0 if timer is configured in 16-bit mode.
R/W
R/W
1/0
31
15
1
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028
This register is used to load the starting count value into the timer. When GPTM is configured to
one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond
to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the
upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR.
R/W
R/W
1/0
30
14
1
TAILRH
TAILRL
Name
R/W
R/W
1/0
29
13
1
R/W
R/W
1/0
28
12
1
Type
R/W
R/W
R/W
R/W
1/0
27
11
1
R/W
R/W
1/0
26
10
1
0xFFFF
0xFFFF
0x0000
(32-bit
mode)
(16-bit
mode)
Reset
R/W
R/W
1/0
25
9
1
Preliminary
Description
GPTM TimerA Interval Load Register High
When configured for 32-bit mode via the GPTMCFG register,
the GPTM TimerB Interval Load (GPTMTBILR) register loads
this value on a write. A read returns the current value of
GPTMTBILR.
In 16-bit mode, this field reads as 0 and does not have an effect
on the state of GPTMTBILR.
GPTM TimerA Interval Load Register Low
For both 16- and 32-bit modes, writing this field loads the
counter for TimerA. A read returns the current value of
GPTMTAILR.
R/W
R/W
1/0
24
8
1
TAILRH
TAILRL
R/W
R/W
1/0
23
7
1
R/W
R/W
1/0
22
6
1
R/W
R/W
1/0
21
5
1
R/W
R/W
1/0
20
4
1
R/W
R/W
1/0
19
3
1
R/W
R/W
1/0
18
2
1
February 6, 2007
R/W
R/W
1/0
17
1
1
R/W
R/W
1/0
16
0
1
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