LM3S2965 Luminary Micro, Inc, LM3S2965 Datasheet - Page 414
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LM3S2965
Manufacturer Part Number
LM3S2965
Description
Lm3s2965 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S2965.pdf
(599 pages)
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Reset
Reset
Type
Type
Inter-Integrated Circuit (I
I2C Slave Interrupt Mask (I2CSIMR)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x00C
Type R/W, reset 0x0000.0000
414
Bit/Field
31:1
0
RO
RO
31
15
0
0
Register 13: I
This register controls whether a raw interrupt is promoted to a controller interrupt.
RO
RO
30
14
0
0
reserved
RO
RO
DATAIM
29
13
0
0
Name
2
C) Interface
RO
RO
28
12
0
0
2
C Slave Interrupt Mask (I2CSIMR), offset 0x00C
RO
RO
27
11
0
0
Type
R/W
RO
RO
RO
26
10
0
0
Reset
0x00
RO
RO
25
0
9
0
0
Preliminary
reserved
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Data Interrupt Mask
This bit controls whether the raw interrupt for data received and data
requested is promoted to a controller interrupt. If set, the interrupt is not
masked and the interrupt is promoted; otherwise, the interrupt is masked.
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
RO
RO
18
0
2
0
July 25, 2008
RO
RO
17
0
1
0
DATAIM
R/W
RO
16
0
0
0
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