LM3S6938 Luminary Micro, Inc, LM3S6938 Datasheet - Page 9

• Manufacturer Part Number: LM3S6938
• Description: Lm3s6938 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Figure 15-3.
Figure 15-4.
Figure 15-5.
Figure 15-6.
Figure 15-7.
Figure 15-8.
Figure 15-9.
Figure 15-10. Master Burst RECEIVE .................................................................................................. 386
Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 387
Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 388
Figure 15-13. Slave Command Sequence ............................................................................................ 389
Figure 16-1.
Figure 16-2.
Figure 16-3.
Figure 17-1.
Figure 17-2.
Figure 17-3.
Figure 18-1.
Figure 18-2.
Figure 21-1.
Figure 21-2.
Figure 21-3.
Figure 21-4.
Figure 21-5.
Figure 21-6.
Figure 21-7.
Figure 21-8.
Figure 21-9.
Figure 21-10. JTAG TRST Timing ........................................................................................................ 511
Figure 21-11. External Reset Timing (RST) .......................................................................................... 512
Figure 21-12. Power-On Reset Timing ................................................................................................. 513
Figure 21-13. Brown-Out Reset Timing ................................................................................................ 513
Figure 21-14. Software Reset Timing ................................................................................................... 513
Figure 21-15. Watchdog Reset Timing ................................................................................................. 513
Figure 22-1.
Figure 22-2.
July 25, 2008
START and STOP Conditions ......................................................................................... 379
Complete Data Transfer with a 7-Bit Address ................................................................... 380
R/S Bit in First Byte ........................................................................................................ 380
Data Validity During Bit Transfer on the I
Master Single SEND ...................................................................................................... 383
Master Single RECEIVE ................................................................................................. 384
Master Burst SEND ....................................................................................................... 385
Ethernet Controller Block Diagram .................................................................................. 414
Ethernet Controller ......................................................................................................... 414
Ethernet Frame ............................................................................................................. 416
Analog Comparator Module Block Diagram ..................................................................... 458
Structure of Comparator Unit .......................................................................................... 459
Comparator Internal Reference Structure ........................................................................ 460
100-Pin LQFP Package Pin Diagram .............................................................................. 470
108-Ball BGA Package Pin Diagram (Top View) ............................................................... 471
Load Conditions ............................................................................................................ 502
I
External XTLP Oscillator Characteristics ......................................................................... 507
Hibernation Module Timing ............................................................................................. 508
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 509
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 509
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 510
JTAG Test Clock Input Timing ......................................................................................... 511
JTAG Test Access Port (TAP) Timing .............................................................................. 511
100-Pin LQFP Package .................................................................................................. 514
108-Ball BGA Package .................................................................................................. 516
2
C Timing ..................................................................................................................... 505
Preliminary
2
C Bus ............................................................... 380
LM3S6938 Microcontroller
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