LM3S1439 Luminary Micro, Inc, LM3S1439 Datasheet - Page 164
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LM3S1439
Manufacturer Part Number
LM3S1439
Description
Lm3s1439 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S1439.pdf
(544 pages)
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General-Purpose Input/Outputs (GPIOs)
9.1.1
9.1.1.1
9.1.1.2
164
Figure 9-1. GPIO Port Block Diagram
Data Control
The data control registers allow software to configure the operational modes of the GPIOs. The data
direction register configures the GPIO as an input or an output while the data register either captures
incoming data or drives it out to the pads.
Data Direction Operation
The GPIO Direction (GPIODIR) register (see page 172) is used to configure each individual pin as
an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and
the corresponding data register bit will capture and store the value on the GPIO port. When the data
direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit
will be driven out on the GPIO port.
Data Register Operation
To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the
GPIO Data (GPIODATA) register (see page 171) by using bits [9:2] of the address bus as a mask.
This allows software drivers to modify individual GPIO pins in a single instruction, without affecting
the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write
operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA
register covers 256 locations in the memory map.
During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA
register is altered. If it is cleared to 0, it is left unchanged.
Alternate Input
Alternate Output
Alternate Output Enable
Interrupt
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIOLOCK
GPIODATA
GPIODIR
GPIORIS
GPIOMIS
GPIOICR
Interrupt
GPIOIBE
GPIOIEV
GPIOCR
Commit
Control
Control
Control
GPIOIM
GPIOIS
Data
Identification Registers
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIO Input
GPIO Output
GPIO Output Enable
GPIOAFSEL
GPIODR2R
GPIODR4R
GPIODR8R
GPIOODR
GPIOPUR
GPIOPDR
GPIODEN
GPIOSLR
Control
Control
Mode
Pad
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
Preliminary
Pad Input
Pad Output
Pad Output Enable
I/O Pad
Digital
July 25, 2008
Package I/O Pin
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