ADP3209 ON Semiconductor, ADP3209 Datasheet - Page 30

• Manufacturer Part Number: ADP3209
• Description: 5-bit, Programmable, Single-phase, Synchronous Buck Controller
• Manufacturer: ON Semiconductor

ADP3209
7.
8.
9.
Set the Initial Transient
1.
2.
be necessary to try several parallel values to obtain an
adequate one because there are limited standard capacitor
values available (it is a good idea to have locations for two
capacitors in the layout for this reason).
Repeat Steps 5 and 6 until no adjustment of C
Once this is achieved, do not change C
procedure.
Set the dynamic load step to its maximum step size (but do
not use a step size that is larger than needed) and verify
that the output waveform is square, meaning V
V
Ensure that the load step slew rate and the power-up slew
rate are set to ~150 A/μs to 250 A/μs (for example, a load
step of 50 A should take 200 ns to 300 ns) with no
overshoot. Some dynamic loads have an excessive
overshoot at power-up if a minimum current is incorrectly
set (this is an issue if a VTT tool is in use).
With the dynamic load set at its maximum step size,
expand the scope time scale to 2 μs/div to 5 μs/div. This
results in a waveform that may have two overshoots and
one minor undershoot before achieving the final desired
value after V
If both overshoots are larger than desired, try the following
adjustments in the order shown.
a.
b.
c.
If these adjustments do not change the response, it is
because the system is limited by the output decoupling.
Check the output response and the switching nodes each
DCDRP
Increase the resistance of the ramp resistor
(R
For V
frequency.
For V
C
Figure 39. Transient Setting Waveform, Load Step
CS
RAMP
are equal.
V
(
TRAN1
NEW
TRAN2
TRAN1
) by 25%.
DROOP
)
=
, increase R
, increase C
C
CS
(see Figure 39).
V
TRAN2
(
OLD
)
×
A
B
V
V
by 25% and decrease C
or increase the switching
DCDRP
ACDRP
V
DROOP
CS
for the rest of the
CS
ACDRP
Rev. 2 | Page 30 of 32 | www.onsemi.com
is needed.
A
by 25%.
and
(42)
3.
LAYOUT AND COMPONENT PLACEMENT
The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.
General Recommendations
1.
2.
3.
4.
time a change is made to ensure that the output decoupling
is stable.
For load release (see Figure 40), if V
the value specified by IMVP-6+, a greater percentage of
output capacitance is needed. Either increase the
capacitance directly or decrease the inductor values. (If
inductors are changed, however, it will be necessary to
redesign the circuit using the information from the
spreadsheet and to repeat all tuning guide procedures).
For best results, use a PCB of four or more layers. This
should provide the needed versatility for control circuitry
interconnections with optimal placement; power planes for
ground, input, and output; and wide interconnection traces
in the rest of the power delivery current paths. Keep in
mind that each square unit of 1 oz copper trace has a
resistance of ~0.53 mΩ at room temperature.
When high currents must be routed between PCB layers, vias
should be used liberally to create several parallel current
paths so that the resistance and inductance introduced by
these current paths is minimized and the via current rating
is not exceeded.
If critical signal lines (including the output voltage sense
lines of the ADP3209) must cross through power circuitry,
it is best if a signal ground plane can be interposed between
those signal lines and the traces of the power circuitry. This
serves as a shield to minimize noise injection into the
signals at the expense of increasing signal ground noise.
An analog ground plane should be used around and under
the ADP3209 for referencing the components associated
with the controller. This plane should be tied to the nearest
ground of the output decoupling capacitor, but should not
be tied to any other power circuitry to prevent power
currents from flowing into the plane.
Figure 40. Transient Setting Waveform, Load Release
V
TRANREL
V
DROOP
TRANREL
is larger than