LM1236 National Semiconductor Corporation, LM1236 Datasheet - Page 32

• Manufacturer Part Number: LM1236
• Description: 150 Mhz I2c Compatible Rgb Preamplifier With Internal 254 Character Osd Rom, 512 Character Ram And 4 Dacs
• Manufacturer: National Semiconductor Corporation

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Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 7
Bits 4–0
Bits 7–5
Building Display Pages
Control Register Definitions
OSD INTERFACE REGISTERS
Frame Control Register 1:
Frame Control Register 2:
On-Screen Display Enable. The On-Screen Display will be disabled when this bit is a zero. When this bit is a one
the On-Screen Display will be enabled. This controls both Window 1 and Window 2.
Display Window 1 Enable. When this bit and Bit 0 of this register are both ones, Display Window 1 is enabled. If
either bit is a zero, then Display Window 1 will be disabled.
Display Window 2 Enable. When this bit and Bit 0 of this register are both ones, Display Window 2 is enabled. If
either bit is a zero, then Display Window 2 will be disabled.
Clear Display Page RAM. Writing a one to this bit will result in setting all of the Display Page RAM values to zero.
This bit is automatically cleared after the operation is complete. This bit is initially asserted by default at power up,
and will clear itself back to zero shortly after. Thus, the default value is one only momentarily, and then will remain
zero until manually asserted again or until the power is cycled.
Transparent Disable. When this bit is a zero, a palette color of black (i.e., color palette look-up table value of 0x00)
in the first 8 palette look-up table address locations (i.e., ATT0–ATT7) will be interpreted as transparent. When this
bit is a one, the color will be interpreted as black.
Fade In/Out Enable. When this bit is a 1, the OSD Fade In/Fade Out function is enabled. When this bit is a 0, the
function is disabled.
Half Tone Disable. When this bit is a 1, the OSD Half Tone Transparency function is disabled. When this bit is a 0,
the half tone transparency is enabled.
Blinking Period. These five bits set the blinking period of the blinking feature, which is determined by mulitiplying
the value of these bits by 8, and then multiplying the result by the vertical field rate.
Pixels per Line. These three bits determine the number of pixels per line of OSD characters. See Table 24 which
gives the maximum horizontal scan rate. Also see Table 3 since the maximum recommended scan rate is also a
function of the PLLFREQRNG register, 0x843E[1:0].
Bits 7–5
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
halftone
HTD
Pixels per Line
PL[2:0]
X
TABLE 23. Sequence of Transmitted Bytes
(Continued)
TABLE 24. OSD Pixels per Line
Fade
FEN
i/o
FRMCTRL1 (0x8400)
FRMCTRL2 (0x8401)
1024 pixels per line
1088 pixels per line
1152 pixels per line
704 pixels per line
768 pixels per line
832 pixels per line
896 pixels per line
960 pixels per line
Description
trans
TD
32
CDPR
clear
Blink Period
BP[4:0]
win2
D2E
win1
D1E
Max Horizontal Frequency (kHz)
OSD
OsE
110
110
110
110
110
108
102
96