IRCC2.0 SMSC Corporation, IRCC2.0 Datasheet - Page 73

• Manufacturer Part Number: IRCC2.0
• Description: Infrared Communications Controller
• Manufacturer: SMSC Corporation

second service request was not enough data to
exceed the FIFO Threshold given the long
DMA
The DMA channel works in Single-Byte and
Burst (Demand) Mode. AEN is high during DMA
transfers. The DMA controls are located in SCE
Configuration Register B.
Enable bit (D0) is one, DMA is enabled. The
DMA Burst Mode bit (D1) controls the DMA
mode. DRQ is further gated by the SCE Modes
bits; e.g., DRQ can only be enabled if either
Transmit or Receive mode has been enabled.
During transmit DRQ remains active as long as
Data Bytes in FIFO 51
FIFO Int. Enable
FIFO Interrupt
TxServReq
DMA Enable
DMA Burst
FIGURE 38 - DMA SINGLE-BYTE MODE TIMING
nDACK
FIGURE 37 - FIFO INTERRUPT EXAMPLE
1st Service
Request
When the DMA
DRQ
AEN
50
I/Ox
TC
Service Req.
49
Satisfied
54
...
51
2nd Service
73
Request
50
interrupt latency.
the FIFO is not full until TC. During receive DRQ
remains active as long as the FIFO is not empty
until TC.
Single-Byte Mode
Single-Byte mode is enabled by resetting the
DMA Burst bit in SCE Configuration Register B.
Single-Byte DMA transfers one data byte for
each DRQ (Figure 38). Terminal Count occurs
only once, during the last byte of the data block.
49
48
47
46
Serv. Req. Satisfied
(long int. latency)
45
44
49
3rd Service
Request
48
...