AD8315ARM Analog Devices, AD8315ARM Datasheet - Page 10

• Manufacturer Part Number: AD8315ARM
• Description: Controllers, 50dB GSM PA Controller
• Manufacturer: Analog Devices

AD8315
Control Loop Dynamics
In order to understand how the AD8315 behaves in a complete
control loop, an expression for the current in the integration
capacitor as a function of the input V
V
First, the summed detector currents are written as a function of
the input:
where I
exact average value will be extracted through the subsequent
integration step; I
of 115 mA per decade (that is, 5.75 mA/dB); V
volts-rms; and V
previously noted, is dependent on waveform but is 316 mV rms
(–70 dBV) for a sine wave input. Now the current generated by
the setpoint interface is simply:
The difference between this current and I
loop filter capacitor C
this capacitor, V
The control output V
gain of the output buffer is ¥1.35. Also, an offset voltage is
deliberately introduced in this stage; this is inconsequential
since the integration function implicitly allows for an arbitrary
constant to be added to the form of Equation 6. The polarity is
such that V
V
V
unless the control loop through the power amplifier is present.
In other words, the AD8315 seeks to drive the RF power to its
maximum value whenever it falls below the setpoint. The use
of exact integration results in a final error that is theoretically
zero, and the logarithmic detection law would ideally result in a
constant response time following a step change of either the
setpoint or the power level, if the power-amplifier control
function were likewise linear-in-dB. This latter condition is
rarely true, however, and it follows that in practice, the loop
response time will depend on the power level, and this effect can
strongly influence the design of the control loop.
Equation 6 can be restated as:
SET
SET
APC
V
V
I
I
=
must be developed. Refer to Figure 3.
output will rail to the positive supply under this condition
greater than the equivalent value of V
DET
SET
FLT
RFIN
APC
V
V
DET
SET
3
1
SET
Figure 3. Behavioral Model of the AD8315
( ) (
( )
=
V
=
V
s
s
IN
SET
is the partially filtered demodulated signal, whose
APC
V
I
/ .
SLP
=
4 15
=
SET
V
I
DET
will rise to its maximum value for any value of
I
FLT
RF DETECTION
log (
SET
SET
INTERFACE
LOGARITHMIC
/ . 4 15
SETPOINT
Z
SUBSYSTEM
SLP
k
= I
is the effective intercept voltage, which, as
, is the time integral of the difference current:
10
W
SLP
-
–
is the current-mode slope and has a value
FLT
APC
–
V
V V
I
LOG
k
DET
sC
SLP
I
IN
W
. It follows that the voltage appearing on
SLP
is slightly greater than this, since the
10
/
FLT
)/
log (
(V
sT
Z
sC
log
IN
I
)
SET
I
DET
/V
10
FLT
Z
10
)
= V
V V
(
SET
I
IN
V
ERR
IN
IN
/
/4.15k
FLTR
/
Z
and the setpoint voltage
V
4
)
DET
Z
C
IN
)
FLT
. In practice, the
IN
is applied to the
1.35
is the input in
VAPC
7
(3)
(4)
(5)
(6)
(7)
–10–
where V
a value of 480 mV/decade, and T is an effective time constant for
the integration, being equal to 4.15 kW ¥ C
value comes from the setpoint interface scaling Equation 4 and
the factor 1.35 arises because of the voltage gain of the buffer.
So the integration time constant can be written as:
To simplify our understanding of the control loop dynamics,
begin by assuming that the power amplifier gain function actu-
ally is linear-in-dB. Also use voltages to express the signals at
the power amplifier input and output, for the moment. Let the
RF output voltage be V
characterize the gain control function, this form is used:
where G
V
conveniently to this law, it provides a clearer starting point for
understanding the more complex situation that arises when the
gain control law is less ideal.
This idealized control loop is shown in Figure 4. With some
manipulation, it is found that the characteristic equation of this
system is:
where k is the coupling factor from the output of the power
amplifier to the input of the AD8315 (e.g., ¥ 0.1 for a “20 dB
coupler”), and T
This is quite easy to interpret. First, it shows that a system of
this sort will exhibit a simple single-pole response, for any power
level, with the customary exponential time domain form for
either increasing or decreasing step polarities in the demand
level V
final value of the control voltage V
several fixed factors:
Example
Assume that the gain magnitude of the power amplifier runs
from a minimum value of ¥0.316 (–10 dB) at V
(40 dB) at V
V
30 dB directional coupler) and recalling that the nominal value of
V
the range of values needed for V
of 33 dBm to –17 dBm. This can be found by noting that, in
the steady state, the numerator of Equation 7 must be zero,
that is:
when V
the power amplifier output. Now, for +33 dBm, V
this evaluates to:
For a delivered power of –17 dBm, V
GBC
GBC
SLP
V
V
V
V
V
SET
SET
SET
APC
V
T
APC
is 480 mV and V
is the gain-scaling. While few amplifiers will conform so
= 1 V. Using a coupling factor of k = 0.0316 (that is, a
PA
SET
(
(
= 3 07
IN
(
=
SLP
( )
max =
min =
O
t
=
s
V
is expanded to kV
is the gain of the power amplifier when V
or the carrier input V
= •
.
G V
SLP
is the volts-per-decade slope from Equation 1, having
=
)
APC
)
O CW
(
)
V
C
log (
0 48
=
SET
FLT
0 48
= 2.5 V. Applying Equation 9, G
.
O
(
.
V
is a modified time constant (V
10
10
V
SET
in s when C is
log (
GBC
(
V
kV
log
Z
m
APC
V
PA
= 316 V for the AD8315, first calculate
10
GBC
)/
PA
10
,
/
V
and its input be V
V
GBC
/
1
(
V
SLP
PA
)
316
mV
)
/
Z
, the fractional voltage sample of
V
)
CW
–
SLP
SET
1
/
V
mV
316
+
. Second, it reveals that the
APC
GBC
sT
to control an output range
– log
expressed
/
O
will be determined by
316
m
log
PA
V
10
= 31.6 mV rms:
10
)
(
m
FLT
=
kG V
(
CW
V
kG V
0 24
APC
in nF
/1.35; the resistor
O
.
)
. Further, to
O
=
PA
GBC
= 0 to ¥100
O
CW
1 44
V
CW
= 10 V rms,
= 0.316 and
APC
.
/V
/
/
V
V
SLP
V
= 0 and
Z
Z
REV. B
)
)
)T.
(11)
(10)
(12)
(13)
(14)
(8)
(9)