MIC2586R Micrel Semiconductor, MIC2586R Datasheet - Page 12
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MIC2586R
Manufacturer Part Number
MIC2586R
Description
Positive High-Voltage Hot Swap Controller /Sequencer
Manufacturer
Micrel Semiconductor
Datasheet
1.MIC2586R.pdf
(17 pages)
Available stocks
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removed/cycled, or c) the ON pin is toggled LOW then HIGH.
The duty cycle of the auto-restart function is therefore fixed
at 5% and the period of the auto-restart cycle is given by:
The auto-restart period for the example above where the
worse-case C
Input Undervoltage Lockout
The MIC2586/MIC2586R have an internal undervoltage
lockout circuit that inhibits operation of the controller’s
internal circuitry unless the power supply voltage is stable
and within an acceptable tolerance. If the supply voltage to
the controller with respect to ground is greater than the V
threshold voltage (8V typical), the controller’s internal circuits
are enabled and the controller is then ready for normal
operation pending the state of the ON pin voltage. Once in
steady-state operation, the controller’s internal circuits
remain active so long as the supply voltage with respect to
ground is higher than the controller’s internal V
voltage (7.5V typical).
Power-is-Good Output Signals
For the MIC2586-1/MIC2586R-1, power-good output signal
PWRGD1 will be high impedance when the FB pin voltage is
higher than the V
when the FB pin voltage is lower than the V
the MIC2586-2/MIC2586R-2, power-good output signal
/PWRGD1 will pull down to GND when the FB pin voltage is
higher than the V
when the FB pin voltage is lower than the V
Hence, the (-1) parts have an active-HIGH PWRGDx signal
and the (-2) parts have an active-LOW /PWRGDx output.
PWRGDx (or /PWRGDx) may be used as an enable signal
for one or more DC/DC converter modules or for other
system functions. When used as an enable signal, the time
necessary for the PWRGDx (or /PWRGDx) signal to pull-up
(when in high impedance state) will depend upon the (RC)
load at the respective Power-is-Good pin.
Micrel
October 2004
t
t
t
AUTO_RESTA
AUTO
AUTO
t
AUTO-RESTART
-
-
RESTART
RESTART
TIMER
RT
FBH
FBH
was calculated to be 3.3µF is:
=
=
=
= 825ms
20
C
20
TIMER
threshold and will be high impedance
threshold and will pull down to GND
×
×
t
(
C
FLT_AUTO
TIMER
×
⎛
⎜ ⎜
⎝
250
) (
×
ms
µ
I
V
TIMERUP
F
TIMERH
⎞
⎟ ⎟
⎠
−
V
FBL
TIMERL
threshold. For
FBL
UVL
)
threshold.
threshold
(7)
UVH
12
Power-is-Good output signals PWRGD2 (/PWRGD2) and
PWRGD3 (/PWRGD3) are asserted after the assertion of
PWRGD1 (/PWRGD1) by a user-programmable time delay
set by an external capacitor (C
PGTIMER pin (Pin 7) to GND. An expression for the time
delay to assert PWRGD2 (or /PWRGD2) after PWRGD1 (or
/PWRGD1) asserts is given by:
where V
/PWRGD2) threshold voltage for PGTIMER and I
typically) is the internal PGTIMER pin charging current.
Similarly, an expression for the time delay to assert
PWRGD3 (or /PWRGD3) after PWRGD1 (or /PWRGD1)
asserts is given by:
where V
threshold voltage for PGTIMER. Therefore, PWRGD2 (or
/PWRGD2) will be delayed after the assertion of PWRGD1
(or /PWRGD1) by:
PWRGD3 (/PWRGD3) follows the assertion of PWRGD1
(/PWRGD1) by a delay:
For example, for a C
will be asserted 9ms after PWRGD1 (or /PWRGD1).
PWRGD3 (or /PWRGD3) will then be asserted 9ms after
PWRGD2 (or /PWRGD2) and 18ms after the assertion of
PWRGD1 (or /PWRGD1). The relationships between V
V
Figures 5 and 6.
Each Power-is-Good output pin is connected to an open-
drain, N-channel transistor implemented with high-voltage
structures. These transistors are capable of operating with
pull-up resistors to supply voltages as high as 100V.
FBH
t
t
t
, PWRGD1, PWRGD2, and PWRGD3 are shown in
PG(1
PG(1
PG(1
t
PG(1
−
−
−
PG3
2)
2)
3)
PG2
(ms)
(ms)
−
=
3)
(1.25V, typically) is the PWRGD3 (or /PWRGD3)
C
I
CPG
=
PG
≅
≅
(0.625V, typically) is the PWRGD2 (or
I
C
CPG
180
PG
90
×
V
×
×
PG2
×
C
V
C
PG
PG
PG3
PG
(
µ
of 0.1µF, PWRGD2 (or /PWRGD2)
(
F)
µ
F)
PG
) from the controller's
MIC2586/MIC2586R
www.DataSheet4U.com
(408) 955-1690
M9999-102204
CPG
(8)
(9)
(7µA,
OUT
,