AD8197A Analog Devices, AD8197A Datasheet - Page 18

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AD8197A

Manufacturer Part Number
AD8197A
Description
4:1 HDMI/DVI Switch with Equalization
Manufacturer
Analog Devices
Datasheet

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AD8197A
SERIAL INTERFACE CONFIGURATION REGISTERS
The serial interface configuration registers can be read and written using the I
The least significant bits of the AD8197A I
3.3 V (Logic 1) or 0 V (Logic 0). As soon as the serial control interface is used, the parallel control interface is disabled until the AD8197A
is reset, as described in the Serial Control Interface section.
Table 5. Serial (I
Name
High Speed
Device
Modes
Auxiliary
Device
Modes
Receiver
Settings
Input
Termination
Pulse
Register 1
Input
Termination
Pulse
Register 2
Receive
Equalizer 1
Receive
Equalizer 2
Transmitter
Settings
Bit 7
RX_PT[7]
RX_PT[15]
RX_EQ[7]
RX_EQ[15]
2
C) Interface Register Map
Bit 6
High
speed
channel
enable
HS_EN
Auxiliary
switch
enable
AUX_EN
RX_PT[6]
RX_ PT[14]
RX_EQ[6]
RX_EQ[14]
Source C and Source D : input termination pulse-on-source switch select
Source A and Source B : input termination pulse-on-source switch select
Bit 5
0
0
RX_PT[5]
RX_PT[13]
RX_EQ[5]
RX_EQ[13]
Source A and Source B: input equalization level select
Source C and Source D: input equalization level select
2
C part address are set by tying Pin I2C_ADDR2, Pin I2C_ADDR1, and Pin I2C_ADDR0 to
(disconnect termination for a short period of time)
(disconnect termination for a short period of time)
Bit 4
0
0
RX_PT[4]
RX_PT[12]
RX_EQ[4]
RX_EQ[12]
Rev. 0 | Page 18 of 28
Bit 3
0
0
RX_PT[3]
RX_PT[11]
RX_EQ[3]
RX_EQ[11]
TX_PE[1]
High speed output
pre-emphasis level
select
2
C serial control interface, Pin I2C_SDA, and Pin I2C_SCL.
Bit 2
0
0
RX_PT[2]
RX_PT[10]
RX_EQ[2]
RX_EQ[10]
TX_PE[0]
Bit 1
HS_CH[1]
AUX_CH[1]
RX_PT[1]
RX_PT[9]
RX_EQ[1]
RX_EQ[9]
High speed
output
termination
select
TX_PTO
Auxiliary switch source select
High speed source select
Bit 0
HS_CH[0]
AUX_CH[0]
High speed
channel
input
termination
select
RX_TO
RX_PT[0]
RX_PT[8]
RX_EQ[0]
RX_EQ[8]
High speed
output
current level
select
TX_OCL
Addr.
0x00
0x01
0x10
0x11
0x12
0x13
0x14
0x20
Default
0x40
0x40
0x01
0x00
0x00
0x00
0x00
0x03

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