AD8150 Analog Devices, AD8150 Datasheet - Page 19

• Manufacturer Part Number: AD8150
• Description: Xstream 33 17, 1.5 Gbps Digital Crosspoint Switch
• Manufacturer: Analog Devices

REV. 0
Power Supplies
There are several options for the power supply voltages for the
AD8150, as there are two separate sections of the chip that require
power supplies. These are the control logic and the high-speed
data paths. Depending on the system architecture, the voltage
levels of these supplies can vary.
Logic Supplies
The control (programming) logic is CMOS and is designed to
interface with any of the various standard single-ended logic
families (CMOS or TTL). Its supply voltage pins are V
170, logic positive) and V
the logic ground should be connected to the system digital ground.
V
supply voltage of the logic family that is used to drive the logic
inputs. V
capacitor. The absolute maximum voltage from V
is 5.5 V.
Data Path Supplies
The data path supplies have more options for their voltage lev-
els. The choices here will affect several other areas, like power
dissipation, bypassing, and common mode levels of the inputs
and outputs. The more positive voltage supply for the data paths
is V
V
The maximum allowable voltage across these supplies is 5.5 V.
The first choice in the data path power supplies is to decide
whether to run the device as ECL (Emitter-Coupled Logic) or
PECL (Positive ECL). For ECL operation, V
potential, while V
to –5 V. This will make the common-mode voltage of the inputs
and outputs at a negative voltage, see Figure 37.
If the data paths are to be dc-coupled to other ECL logic devices
that run with ground as the most positive supply and a negative
voltage for V
DD
EE
CC
, which appears on many pins that will not be listed here.
0.1 F
should be supplied at between 3.3 V to 5 V to match the
Figure 37. Power Supplies and Bypassing for ECL
Operation
AD8150
(Pins 41, 98, 149 and 171). The more negative supply is
DD
CONTROL
3V TO 5V
LOGIC
should be bypassed to ground with a 0.1 µF ceramic
EE
GND
, then this is the proper way to run. However, if
V
V
SS
DD
EE
will be at a negative supply between –3.3 V
PATHS
SS
DATA
3V TO 5V
GND
(Pin 152, logic ground). In all cases
V
V
EE
CC
0.1 F
(ONE FOR EVERY TWO V
CC
will be at ground
DD
EE
to V
DD
PINS)
(Pin
SS
–19–
the part is to be ac coupled, it is not necessary to have the input/
output common mode at the same level as the other system cir-
cuits, but it will probably be more convenient to use the same
supply rails for all devices.
For PECL operation, V
will be a positive voltage from 3.3 V to 5 V. Thus, the common
mode of the inputs and outputs will be at a positive voltage.
These can then be dc coupled to other PECL operated devices.
If the data paths are ac coupled, then the common-mode levels
do not matter, see Figure 38.
POWER DISSIPATION
For analysis, the power dissipation of the AD8150 can be divided
into three separate parts. These are the control logic, the data
path circuits and the (ECL or PECL) outputs, which are part of
the data path circuits, but can be dealt with separately. The first
of these, the control logic, is CMOS technology and does not
dissipate a significant amount of power. This power will, of
course, be greater when the logic supply is 5 V rather than 3 V,
but overall it is not a significant amount of power and can be
ignored for thermal analysis.
The data path circuits operate between the supplies V
V
range from 3.3 V to 5 V. The current consumed by this section
will be constant, so operating at a lower voltage can save about
40 percent in power dissipation.
EE
0.1 F
. As described in the power supply section, this voltage can
Figure 38. Power Supplies and Bypassing for PECL
Operation
AD8150
Figure 39. Major Power Consumption Paths
AD8150
CONTROL
3V TO 5V
LOGIC
GND
CONTROL
V
V
LOGIC
SS
DD
GND
V
V
I, DATA PATH
LOGIC
DD
SS
EE
3V TO 5V
V
PATHS
DATA
CC
GND
will be at ground potential and V
V
V
EE
EE
PATHS
GND
DATA
V
CC
0.1 F
(ONE FOR EACH V
I
OUT
V
OUT
LOW – V
AD8150
CC
R
OUT
PIN, 4 REQ'D.)
EE
CC
and
CC