SSM-2120 Analog, SSM-2120 Datasheet - Page 4

• Manufacturer Part Number: SSM-2120
• Description: (SSM-2122) Dynamic Range Processors/Dual VCA
• Manufacturer: Analog

SSM2120/SSM2122
TRIMMING THE VCAs
The control feedthrough (CFT) pins are optional control feed-
through null points. CFT nulling is usually required in applications
such as noise gating and downward expansion. If trimming is
not used, leave the CFT pins open.
Trim Procedure
1. Apply a 100 Hz sine wave to the control point attenuator.
2. Adjust the 50 k potentiometer for the minimum
(Trimmed control feedthrough is typically well under 1 mV rms
when the maximum gain is unity using 36 k input and output
resistors.)
Applications such as compressor/limiters typically do not require
control feedthrough trimming because the VCA operates at
unity-gain unless the signal is large enough to initiate gain
reduction. In this case the signal masks control feedthrough.
This trim is ineffective for voltage-controlled filter applications.
LEVEL DETECTION CIRCUITS
The SSM2120 contains two independent level detection
circuits. Each circuit contains a wide dynamic range full-wave
rectifier, logging circuit and a unipolar drive amplifier. These
circuits will accurately detect the input signal level over a
100 dB range from 30 nA to 3 mA peak-to-peak.
LEVEL DETECTOR THEORY OF OPERATION
Referring to the level detector block diagram of Figure 3, the
REC
ments the full-wave rectification of the input current. This
current is then fed into a logging transistor (Q
transistor (Q
AV output is then:
With the use of the LOG AV capacitor the output is then the log
of the average of the absolute value of I
(The unfiltered LOG AV output has broad flat plateaus with
sharp negative spikes at the zero crossing. This reduces the
“work” that the averaging capacitor must do, particularly at low
frequencies.)
The signal peaks should correspond to the control voltages
which induce the VCAs maximum intended gain and at least
30 dB of attenuation.
feedthrough.
IN
input is an AC virtual ground. The next block imple-
2
) has a fixed collector current of I
V
LOG
INPUT
AV
R
kT
IN
q
ln
REC
|I
IN
I
IN
REF
.
IN
|
1
2V
) whose pair
REF
. The LOG
Figure 3. Level Detector
RECTIFIER
WAVE
FULL
C
AV
–4–
|I
I N
|
Q1
Note: It is natural to assume that with the addition of the
averaging capacitor, the LOG AV output would become the
average of the log of the absolute value of I
capacitor forces an ac ground at the emitter of the output
transistor, the capacitor charging currents are proportional to
the antilog of the voltage at the base of the output transistor.
Since the base voltage of the output transistor is the log of the
absolute value of I
capacitor becomes a linear integrator with a charging current
directly proportional to the absolute value of the input current.
This effectively inverts the order of the averaging and logging
functions. The signal at the output therefore is the log of the
average of the absolute value of I
USING DETECTOR PINS REC
CON
When applying signals to REC
resistor should be followed by a low leakage blocking capacitor
since REC
ground. Choose R
operation this corresponds to a value of 10 k .
A 1.5 M value of R
a 10 A reference current in the logging transistor (Q
will bias the transistor in the middle of the detector’s dynamic
current range in dB to optimize dynamic range and accuracy.
The LOG AV outputs are buffered and amplified by unipolar
drive op amps. The 39 k , 1 k resistor network at the
THRESH pin provides a gain of 40.
An attenuator from the CON
appropriate VCA control port establishes the control sensitivity.
Use 200
R
capacitive loads on the control outputs CON
or capacitive loads are present, it is best to connect the series
resistor R
DYNAMIC LEVEL DETECTOR CHARACTERISTICS
Figures 4 and 5 show the dynamic performance of the level
detector to a change in signal level. The input to the detector (not
shown) is a series of 500 ms tone bursts at 1 kHz in successive
10 dBV steps. The tone bursts start at a level of –60 dBV (with
R
step. Tone bursts range from –60 dBV to +10 dBV. Figure 4
shows the logarithmic level detector output. The output of the
detector is 3 mV/dB at LOG AV and the amplifier gain is 40
which yields 120 mV/dB. Thus, the output at CON
to increase by 1.2 V for each 10 dBV increase in input level.
CON
IN
V+
Q2
V–
LOG AV
1k
R
= 10 k) and return to –60 dBV after each successive 10 dB
I
REF
REF
OUT
for the desired sensitivity. Care should be taken to minimize
CON
THRESH
IN
for the attenuator resistor to ground and choose
39k
has a dc voltage of approximately 2.1 V above
as closely to the CON
CON
IN
IN
V–
OUT
, the log and antilog terms cancel, so the
for a 1.5 mA peak signal. For 15 V
REF
from log average to –15 V will establish
R
CON
OUT
IN
IN
.
(rectifier input) an input series
200
IN
(control output) to the
, LOG
OUT
TO V
IN
pin as possible.
C
. However, since the
AV
, THRESH AND
OUT
. If long lines
OUT
1
). This
is seen
REV. C