STC62WV1024 STC, STC62WV1024 Datasheet - Page 7

• Manufacturer Part Number: STC62WV1024
• Description: VERY LOW POWER VOLTAGE CMOS SRAM
• Manufacturer: STC

DataSheet4U.com
www.DataSheet4U.com
STC62WV1024
WRITE CYCLE2
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
3. T
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
6. OE is continuously low (OE = V
7.
8. D
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
10. The parameter is guaranteed but not 100% tested.
11. T
ADDRESS
CE1
CE2
WE
D
D
All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.
cycle.
outputs must not be applied.
transitions or after the WE transition, output remain in a high impedance state.
signals of opposite phase to the outputs must not be applied to them.
D
WR
IN
OUT
OUT
OUT
STC
CW
is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
is the read data of next address.
is measured from the later of CE1 going low or CE2 going high to the end of write.
is the same phase of write data of this write cycle.
(1,6)
IL
).
t
AS
DataSheet4U.com
(5)
(5)
t
(4,10)
WHZ
t
AW
7
t
t
t
t
WC
CW
CW
WP
(11)
(11)
(2)
t
DW
t
t
t
WR2
OW
DH
STC62WV1024
(3)
(8,9)
(7)
Revision 2.1
Jan.
(8)
2004