AN2621 Freescale Semiconductor / Motorola, AN2621 Datasheet - Page 7

• Manufacturer Part Number: AN2621
• Description: MPC8220i PF300 Image Coprocessor Operation
• Manufacturer: Freescale Semiconductor / Motorola

two index dimensions, respectively. The additional factor of 4 is required if the normal three-color input
(RGB) to four-color output (CMYK) conversion is being implemented.
The sparse output color lookup table data is stored sequentially in system memory starting at the BaseAdr.
The first 32 bits of the color lookup table contains 1 byte for each of the output colorant values (in this case
C, M, Y, and K) for the first table grid point. The second 32 bits of the colorant lookup table contains the
output colorant values for the second grid point (indexed in the first input dimension) and so forth.
Once the indices are converted to colorant lookup table addresses, the output color data are fetched from the
color lookup table. The vector of remainders is then used to perform the interpolation within the eight
surrounding colorant values to produce an 8-bit colorant value for each output channel for the current pixel.
The interpolation is computed in parallel for each of the output channels.
The last stage of the CCU consists of individual one-dimensional lookup tables for each of the interpolated
output channels. The one-dimensional lookup tables are loaded into a dedicated PF300 memory block
referred to as the CCU output lookup table, which must not be confused with the sparse three-dimensional
colorant lookup table located in system memory and discussed in the preceding paragraph.
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3.1
The Screening Unit (SU) of the PF300 implements a standard threshold array algorithm (See Adobe
Systems Incorporated, PostScript Language Reference Manual, Second Edition, Section 6.4.5 pages
316-317) for halftone screening. A two-dimensional threshold array, also referred to as a tile, memory is
loaded with 8-bit threshold values. Image pixel data is read into the Screening Unit in pixel-by-pixel,
line-by-line (raster) order. With each input pixel the tile memory is addressed modulo (the tile X dimension
size), the threshold value at that address is accessed, and a comparison is made with the current input pixel.
If the input pixel value is less than the corresponding threshold array value then the binary output for that
pixel is set to 1, otherwise it is set to zero. The binary output pixel is then stored in the output buffer, the
next input pixel is input to the block, and the process repeats. At the end of each raster line the Y threshold
array address is incremented and evaluated modulo (the tile Y dimension size) and the entire process
repeats.
The result is a binary image that represents the input gray scale image through area, instead of intensity,
modulation. The threshold array is applied as if it were replicated in a step and repeat fashion across the
entire image.
3.2
The SU in the PF300 Image Coprocessor contains programmable registers for each of the (up to) four screen
tiles to control the following:
MOTOROLA
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X dimension tile size
Y dimension tile size
Start address of the tile in threshold array memory
X dimension starting pixel phase
Y dimension starting pixel phase
The Screening Unit
Algorithm Description
Computational Details
MPC8220i PF300 Image Coprocessor Operation
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The Screening Unit
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