AN2517 Freescale Semiconductor / Motorola, AN2517 Datasheet - Page 18

• Manufacturer Part Number: AN2517
• Description: 3-Phase Sine Wave Generator with Dead-Time Correction TPU Function Set
• Manufacturer: Freescale Semiconductor / Motorola

AN2517/D
18
3-Phase Sine Wave Generator with Dead-Time Correction TPU Function Set (3SinDt) MOTOROLA
When 3SinDt_top and 3SinDt_bottom are running alone on one TPU, the
minimum pulse width can be calculated according to
the worst case timing. The bottom channel low to high transition runs the HL
state that sets the following high to low transition. The HL state lasts 2 IMB
clock cycles (see
(TST), which takes 10 IMB clock cycles. So the time necessary to set the next
transition on the bottom channel is 12 IMB clock cycles. In addition, there is a
latency between the low to high transition and the start of the HL state. The top
channel state LH_C7, which is serviced at the time, causes the latency. The
LH_C7 state lasts 40 IMB clock cycles (see
10 IMB clock cycles. The service starts immediately after the top channel high
to low transition, which occurs at a period of DT before the bottom channel low
to high transition (see
IMB clock cycles – DT. The 3SinDt functions are designed so that no other
3SinDt state can request service at this time. The MPW, in the case when only
3SinDt functions are running on one TPU, is then
and has a minimum value of at least 12 IMB clock cycles (when latency = 0).
Note that the MPW, as well as the DT, are not entered into the parameter
RAM in IMB clock cycles, but in TCR1 clock cycles. It is recommended for
the 3SinDt function that the TCR1 clock is configured for its maximum speed,
which is the IMB clock divided by 2. In this case the MPW = 31 – DT, with a
minimum value of 6.
= 40 IMB clock cycles + 10 IMB clock cycles – DT + 12 IMB clock cycles =
bottom channel
bottom channel
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top channel
top channel
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center_time
center_time
Table
Figure 7. Timing of the worst case
Figure
latency + 12 IMB clock cycles =
10). Each state is preceded by the Time Slot Transition
= 62 IMB clock cycles – DT
7), so that the latency is 40 IMB clock cycles + 10
Table
DT
DT
9). Its time slot transition is
LH_C7
LH_C7
latency
latency
Figure
MPW
MPW
HL
HL
7. This illustrates