AN2475 Freescale Semiconductor / Motorola, AN2475 Datasheet - Page 7

• Manufacturer Part Number: AN2475
• Description: Generating a PWM Signal Modulated by an Analog Input Using the MC68HC908QY4 Microcontroller
• Manufacturer: Freescale Semiconductor / Motorola

Software Description
MOTOROLA
In this application the PWM duty cycle varies from 0 to 100% in accordance
with the voltage applied on the ADC input. Actually PWM duty cycle varies from
approximately 6% to 94% since it is needed to set a PWM resolution limit for
proper operation of the close-loop system. User can redefine the PWM
resolution limit as explained below. The PWM output of timer channel 0 is
proportional to the analog converted value. When the input voltage increases,
the PWM duty cycle increases and vice versa.
The ADC is configured for continuous conversion. The timer module is
configured for buffered PWM signal generation. The software runs in a closed
loop in which the analog input voltage is converted onto a digital data by the
ADC and then compared to a target regulation value previously defined by the
user. The system reaches regulation if the analog input reading is in between
the upper and lower regulation limits also pre-defined by the user. The driver
transistor is a PMOS device. If the ADC value approaches the upper target
limit, the PWM duty cycle is increased (incremented). When the regulated
output voltage is below the target value but above the lower limit the PWM duty
cycle will be decremented. In case of the regulated output voltage being either
over the upper limit or below the lower limit, the PWM period will be either
enlarged or reduced, respectively. Therefore, the software will be seeking a
combination of PWM period and duty cycle to provide a regulated voltage
satisfying the pre-defined tolerances. PWM period checking range is from 256
to a minimum determined by the system resolution, as discussed below. A
software flowchart is shown in
Every time the period value is changed, the PWM duty cycle is redefined to
50%. In this application a PWM resolution limit is set to approximately
6% (lower) and 94% (upper) of period. If the regulation is not reached varying
PWM duty cycle between those limits, period value is altered again. This
sequence is performed until regulation is attained.
The PWM resolution limits are obtained by shifting the period value four times
to the right. Due to this shifting, the minimum possible period value is attained
to guarantee that resolution is 17 (decimal). However, the user can redefine the
PWM resolution limit altering the source by code taking into account the trade-
off between system resolution and minimum period attainable.
Generating a PWM Signal Modulated by an Analog Input
Freescale Semiconductor, Inc.
For More Information On This Product,
Using the MC68HC908QY4 Microcontroller
Go to: www.freescale.com
Figure
4.
Software Description
AN2475/D
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