AN2468 Freescale Semiconductor / Motorola, AN2468 Datasheet - Page 23

• Manufacturer Part Number: AN2468
• Description: Understanding the MPC74
• Manufacturer: Freescale Semiconductor / Motorola

Freescale Semiconductor, Inc.
Adjusting AC Timing Margins
4.2 Adjusting AC Timing Margins Using Hardware
In situations where it is not possible to correct timing margins in software, the only other recourse is to adjust
trace lengths to skew signals. Generally speaking, if the recommendations in Section 1.1, “General Design
Guidelines,” have been followed, then most adjustments to timing margins will be made by adjusting the
lengths of L3 clock or echo clock traces. The following sections briefly describe the main concerns in doing
so for the various SRAM technologies.
4.2.1 Adjusting AC Timing Margins for Pipelined Burst and Late Write
SRAM
Adjusting AC timing margins for pipelined burst and late write SRAMs requires some care because of the
interdependence of read and write timing. It is important to remember that adjusting the feedback loop trace
length while leaving the L3_CLK trace length unchanged only impacts the AC timing margins for data read
accesses, but changing the L3_CLK trace length while leaving the synchronization loop length unchanged
impacts both read and write access AC timing.
The relationship between the relative length of the feedback loop and the associated signals is
straightforward and is shown graphically in Figure 19 and is summarized in Table 9.
MOTOROLA
Understanding the MPC7450 Family L3 Cache Hardware Interface
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