AN2364 Freescale Semiconductor / Motorola, AN2364 Datasheet - Page 18

• Manufacturer Part Number: AN2364
• Description: Using the Table Stepper Motor TPU Function (TSM) with the MPC500 Family
• Manufacturer: Freescale Semiconductor / Motorola

INT tpu_tsm_int_chk
7.7
This routine will read the value of the active interrupt channel in the CISR register. This value is compared
to the input channel to determine a match. A match confirms that the highest priority active interrupt is for
the specific TSM function.
The integer value of TPU_TSM_TRUE or TPU_TSM_FALSE is returned depending upon the result of the
compare.
7.8
This routine will clear the CISR register. This will have the effect of clearing all active interrupts in the CISR
register.
This routine is needed at the end of the initialization routine to cover interrupts which were activated during
initialization. An interrupt handling routine could take care of active interrupts before cancellation. Even if
interrupts are not used with the TPU, these interrupts should be cleared to reduce the danger of a spurious
interrupt being activated.
8
8.1
Like all TPU functions, TSM function performance in an application is to some extent dependent upon the
service time (latency) of other active TPU channels. This is due to the operational nature of the scheduler.
When the TPU is driving a single stepper motor using TSM in two channel mode, and no other TPU
channels are active, the minimum step period is 186 CPU clocks. This is approximately equivalent to 90,000
pulses per second at 16.77 MHz bus speed and 114,000 pulses per second at 20.97 MHz bus speed. In four-
channel mode, the equivalent figures are 234 CPU clocks, 71,000 pulses per second at 16.77 MHz bus and
89,000 pulses per second at 20.97 MHz. When more TPU functions are active, or multiple motors are
implemented, performance decreases - e.g. if two motors were driven in two channel mode (four active TPU
channels) then the maximum pulse rate for each motor would be approximately half that given above.
However, worst-case latency in any TPU application can be closely estimated. To analyze the performance
of an application that appears to approach the limits of the TPU, use the guidelines given in the TPU
reference manual and the information in Table 3 below.
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*tpu -- This is the pointer to the TPU module chosen to run the TSM function. It is a structure of
type (name) TPU3_tag which is defined in m_tpu3.h.
channel -- This is the channel number of the primary TSM master channel. The 16-bit input value
is encoded to match the CISR value (see: tpu_tsm_mas_chan_cier()).
*tpu -- This is the pointer to the TPU module chosen to run the TSM function. It is a structure of
type (name) TPU3_tag which is defined in m_tpu3.h.
•CISR_level -- This is the channel number which should match the assigned interrupt level for the
TSM function. This currently serves no function. However, further development could clear a
specific channel instead of all channels of the CISR register.
INT tpu_tsm_int_chk
void tpu_tsm_cisr_clr
Performance and Use of TSM Function
Performance
Freescale Semiconductor, Inc.
Using the Table Stepper Motor TPU Function
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