AN2347 Freescale Semiconductor / Motorola, AN2347 Datasheet - Page 40

• Manufacturer Part Number: AN2347
• Description: Using an MPC8260 and an MPC7410 with Shared Memory
• Manufacturer: Freescale Semiconductor / Motorola

Required Header File—init_cn.h
Required Header File—init_cn.h
IDMA Parameter RAM Definitions
Instruction and Data Cache Definition
Note: must load into bits 0–15.
Interrupt StackFrame Definitions
40
PPC_ACR: .equ
MBMR:
MDR:
IDMR1:
RCCR:
SIMR_H:
SIMR_L:
CPCR:
IBASE:
DCM:
IBDPTR:
DPR_BUF: .equ
SS_MAX:
STS:
DTS:
ISTATE:
R0_OFFSET:
R1_OFFSET:
R2_OFFSET:
R3_OFFSET:
R4_OFFSET:
R5_OFFSET:
R6_OFFSET:
R7_OFFSET:
R8_OFFSET:
R9_OFFSET:
R10_OFFSET:
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
Using an MPC8260 and an MPC7410 with Shared Memory
0x0028
0x0174
0x0188
0x1024
0x19C4
0x0C1C
0x0C20
0x19C0
0x0000
0x0002
0x0004
0x0006
0x000A
0x000E
0x0016
0x0028
Freescale Semiconductor, Inc.
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(1*4)
(2*4)
(3*4)
(4*4)
(5*4)
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(7*4)
(8*4)
(9*4)
(10*4)
# 60x Bus Arbiter Configuration Register
# Machine B Mode Register
# Memory Data Register
# IDMA1 mask register
# CP configuration register
# SIU interrupt mask register (high)
# SIU interrupt mask register (low)
# CP command register
# IDMA BD Base
# DMA channel mode
# IDMA BD pointer
# IDMA buffer in DPRAM
# Steady-state maximum IDMA transfer size
# Source transfer size
# Destination transfer size
# Internal IDMA state
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# R0 Stack Offset
# R1 Stack Offset
# R2 Stack Offset
# R3 Stack Offset
# R4 Stack Offset
# R5 Stack Offset
# R6 Stack Offset
# R7 Stack Offset
# R8 Stack Offset
# R9 Stack Offset
# R10 Stack Offset
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