GT3200-ABZJ ETC, GT3200-ABZJ Datasheet - Page 26

• Manufacturer Part Number: GT3200-ABZJ
• Description: USB2.0 PJY IC
• Manufacturer: ETC

Revision 1.3 (10-05-04)
7.4
TXDATA[7:0]
DATA[15:8]
TXREADY
DATA[7:0]
TXVALID
TXREADY
VALIDH
DP/DM
TXVALID
CLK30
DP/DM
CLK60
This block receives parallel data bytes placed on the DATA bus and performs the necessary transmit
operations. These operations include parallel to serial conversion, bit stuffing and NRZI encoding.
Upon valid assertion of the proper TX control lines by the SIE and TX State Machine, the TX LOGIC
block will synchronously shift, at either the FS or HS rate, the data to the FS/HS TX block to be
transmitted on the USB cable. Data transmit timing is shown in
TX Logic
Figure 7.5 Transmit Timing for 16-bit Data, Even Byte Count
Figure 7.4 Transmit Timing for a Data Packet (8-bit mode)
PID
SYNC
DATA (0)
PID
SYNC
DATASHEET
DATA
DATA (1)
DATA (2)
21
PID
PID
DATA
DATA
0
DATA
DATA DATA
DATA (3)
DATA (4)
DATA
DATA
1
DATA
2
DATA
Figure
CRC (LO)
CRC
CRC (HI)
DATA
3
DATA
7.4.
CRC
SMSC GT3200, SMSC USB3250
DATA
4
CRC
CRC
HI
CRC
USB2.0 PHY IC
CRC
LO
EOP
EOP