AN2090 Freescale Semiconductor / Motorola, AN2090 Datasheet - Page 14

• Manufacturer Part Number: AN2090
• Description: Using the SC140/SC1400 Enhanced On-Chip Emulator Stopwatch Timer
• Manufacturer: Freescale Semiconductor / Motorola

Verifying Correct Set-up
With these configurations, the F
The PLL should be configured so that the resulting PLL output frequency is in the range specified in the device’s
technical data sheet.
4.2 Setting Up the PLL in Hardware
During the assertion of hardware reset, the values of all the PLL hardware configuration pins are sampled into the
clock control registers (PCTL0 and PCTL1). Thus, the core frequency can be set up at reset by configuring the
jumpers on the SDP board. To set up the PLL for operation at 300 MHz, the jumpers for PLLEN, PDF1, PDF0,
MFI3, and MFI2 should be removed (thereby causing these bits to be asserted). For details on jumper configuration
of SDP, refer to [2].
5
This section describes how to verify that the system is set up correctly and that the emulator stopwatch timer
measurements are as described in Section 2, Setting Up the Stopwatch Timer In an Application, on page 3. The
verification process is based on measuring a specified time period, while also creating an external behavior
(turning on and off an LED) that can be measured independently by a “wall clock” (that is, an independent
stopwatch, such as an oscilloscope).
5.1 Using the LED on the SDP
The implementation described in this section is based on the configuration of the SDP. In SDP, each
emulator is connected to an LED. The following implementation is based on the ability to program the emulator to
toggle the output value on its pins whenever an event is detected by one of the emulator event detection channels.
Our implementation toggles the output value on the
capability requires just a small enhancement to the stopwatch timer software that is presented in Example 6.
5.1.1 Setting Up EE1
The functionality of the emulator pins is controlled through the EOnCE pins control register (EE_CTRL). Figure
10 displays the structure of this register.
In EE_CTRL, the EE1DEF field is set to 00, which signifies an output signal when detected by EDCA1. The
remaining fields in EE_CTRL are irrelevant because they are not used. Example 7 shows the set-up code for EE
control registers.
14
Verifying Correct Set-up
Using the SC140/SC1400 Enhanced On-Chip Emulator Stopwatch Timer, Rev. 1
Fchip
chip
Figure 10. EE Pins Control Register (EE_CTRL)
is calculated as expressed in Equation 3.
=
50MHz
---------------------------------------------- -
4
×
×
⎛
⎝
1
EE1
24
+
pin when the stopwatch timer starts or stops running. This
0
-- -
1
⎞
⎠
=
300Mhz
Freescale Semiconductor
EE1
Equation 3
pin of the