AN1965 Freescale Semiconductor / Motorola, AN1965 Datasheet - Page 2

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AN1965

Manufacturer Part Number
AN1965
Description
Design of Indirect Power Using the 56F800/E
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
Motorola Hybrid Controller Advantages and Features
2.
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This application note presents the concept of the continuous conduction current mode boost PFC with
nominal output power of 180W. The PFC is digitally controlled by a hybrid controller.
The Motorola 56F800/E families are ideal for digital motor control, combining the DSP’s calculation
capability with the MCU’s controller features on a single chip. These controllers offer a wide variety
of dedicated peripherals, such as Pulse Width Modulation (PWM) modules, Analog-to-Digital
Converter (ADC), timers, communication peripherals (SCI, SPI, CAN), on-board Flash and RAM. .
A typical member of the 56F800 family, the 56F805, provides the following peripheral blocks:
The Pulse Width Modulation (PWM) block offers great freedom in its configuration, enabling efficient
control of the AC induction motor.
The PWM block has the following features:
Motorola Hybrid Controller Advantages and Features
Two Pulse Width Modulators (PWMA & PWMB), each with six PWM output; three current
status inputs, and four fault inputs; fault-tolerant design with dead time insertion; and supports
both center- and edge-aligned modes
Two 12-bit, Analog-to-Digital Converters (ADCs), supporting two simultaneous conversions
with dual 4-pin multiplexed inputs; can be synchronized by PWM modules
Two Quadrature Decoders (Quad Dec0 & Quad Dec1), each with four inputs, or two
additional Quad Timers (A & B)
Two dedicated general-purpose Quad Timers totalling six pins: Timer C with two pins and
Timer D with four pins
CAN 2.0 A/B module with 2-pin ports used to transmit and receive
Two Serial Communication Interfaces (SCI0 & SCI1), each with two pins, or four additional
MPIO lines
Serial Peripheral Interface (SPI), with configurable 4-pin port, or four additional
Multi-Purpose I/O (MPIO) lines
Computer Operating Properly (COP) timer
Two dedicated external interrupt pins
Fourteen dedicated MPIO pins and 18 multiplexed MPIO pins
External reset pin for hardware reset
JTAG/On-Chip Emulation (OnCE™)
Software-programmable, Phase Lock Loop (PLL)-based frequency synthesizer for the hybrid
controller core clock
Three complementary PWM signal pairs, or six independent PWM signals
Features of complementary channel operation
Dead time insertion
Separate top and bottom pulse width correction via current status inputs or software
Separate top and bottom polarity control
Edge-aligned or center-aligned PWM reference signals
15 bits of resolution
Half-cycle reload capability
Freescale Semiconductor, Inc.
For More Information On This Product,
Indirect Power Factor Correction
Go to: www.freescale.com

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