AN1902 Freescale Semiconductor / Motorola, AN1902 Datasheet - Page 11

• Manufacturer Part Number: AN1902
• Description: Quad Flat Pack No-Lead (QFN)
• Manufacturer: Freescale Semiconductor / Motorola

Freescale Semiconductor, Inc.
AN1902/D
4.1.3 Plated Through Hole (PTH) Vias
The Plated Through Hole (PTH) recommendation applies to both Motorola MAP QFN
and Robust Design sections. PTH vias, or more commonly known as via holes,
increase the thermal conduction through dielectric layers. PTH vias connect the PCB
thermal pad to any electrically appropriate internal PCB plane(s). Although the cus-
tomer should use a maximum number of PTH vias, they impact the soldering surface
of the PCB thermal pad. PTH vias should be plugged with epoxy or tented with solder
mask to avoid low package stand-off height due to solder wicking into the PTH vias
during the reflow process. For double sided PCB, the untented PTH vias has the
potential for solder to reach the PCB top side and cause secondary reflow, leading to
potential opens and shorts. A recommended via pattern is 0.3mm PTH via drill diame-
ter on 1mm centers. Improved thermal performance can be obtained with a greater
density of vias and larger vias on the same pattern that provides good solderability.
Thermal reliefs on the vias are not recommended.
4.2 Stencil Design Guideline
The thickness of the stencil determines the amount of solder paste deposited onto the
printed circuit board land pattern. Due to the fine pitch and small terminal geometry
used on QFN, care must be taken when printing the solder paste on to the PCB. Too
much solder paste will cause solder bridging during reflow and too little solder paste
will result in insufficient solder. A 5.0 mil thick stainless steel stencil is recommended
for 0.50mm pitch QFN packages. The 0.65mm pitch package can accommodate a 6
mil thick stencil. Stencil thickness has a potential impact on the assembly for leaded
packages that use paste volume as means for compensating for coplanarity. Since
QFN is (most likely) not the only package on the actual production PCB, the recom-
mended stencil thickness for QFN may be thinner than desired. In such case, a step
down stencil is recommended where most of the stencil for the PCB has a typical
thickness, but the area for the QFN would be reduced to 5 - 6 mils depending on the
package pitch.
4.2.1 Thermal Pad Region
An array design (pattern) is recommended in the stencil opening for the thermal pad
region. A large opening (or aperture) in the thermal region allows “scooping” to occur
during screen printing. The squeegee blade bends into the opening when the stencil
aperture is too large, thereby limiting the amount of solder paste printed in that open-
ing.
Figure 13
illustrates this “scooping” effect. Other reasons for segmenting the
thermal regions include minimizing solder standoff mismatch with terminal pads, mini-
mizing solder voids in the thermal region, and minimizing chances of bridging with ter-
minal pads.
MOTOROLA
Quad Flat Pack No-Lead (QFN)
11
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