DS92LV1021 National Semiconductor, DS92LV1021 Datasheet
DS92LV1021
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DS92LV1021 Summary of contents
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... Block Diagrams TRI-STATE ® registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS100110 due to charged cable conditions. The DS92LV1021 output pins may be TRI-STATE ® to achieve a high impedance state. The PLL can lock to frequencies between 16 MHz and 40 MHz. Features ...
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... Block Diagrams (Continued) Functional Description The DS92LV1021 and DS92LV1210 is a 10-bit Serializer / Deserializer chipset designed to transmit data over a heavily loaded differential backplanes at clock speeds from 16 to 40MHz. It may also be used to drive data over Unshielded Twisted Pair (UTP) cable. The chipset has three active states of operation: Initializa- tion, Data Transfer, and Resynchronization ...
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... Powerdown The Powerdown state is a low power sleep mode that the Serializer and Deserializer may use to reduce power when NSID DS92LV1021TMSA DS92LV1210TMSA there is no data to be transferred. Powerdown is entered when PWRDN and REN are driven low on the Deserializer, and when the PWRDN is driven low on the Serializer. In ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage −0. CMOS/TTL Output Voltage −0. Bus LVDS Receiver Input Voltage Bus LVDS Driver Output ...
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Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter DESERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins RI+ and RI−) I Input Current IN SERIALIZER SUPPLY CURRENT (apply to pins DVCC and AVCC) I Serializer ...
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Deserializer Timing Requirements for REFCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t REFCLK Period RFCP t REFCLK Duty Cycle RFDC Ratio of REFCLK to TCLK RFCP TCP Periods t REFCLK Transition ...
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AC Timing Diagrams and Test Circuits FIGURE 1. “Worst Case” Serializer ICC Test Pattern FIGURE 2. “Worst Case” Deserializer ICC Test Pattern FIGURE 3. Serializer Bus LVDS Output Load and Transition Times FIGURE 4. Deserializer CMOS/TTL Output Load and Transition ...
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AC Timing Diagrams and Test Circuits Timing shown for TCLK_R/F = LOW FIGURE 7. Serializer TRI-STATE Test Circuit and Timing FIGURE 8. Serializer PLL Lock Time, SYNC Timing and PWRDN TRI-STATE Delays www.national.com (Continued) DS100110-8 FIGURE 6. Serializer Setup/Hold Times ...
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AC Timing Diagrams and Test Circuits Timing shown for RCLK_R/F = LOW Duty Cycle ( RDC FIGURE 11. Deserializer Setup and Hold Times (Continued) FIGURE 9. Serializer Delay FIGURE 10. Deserializer Delay DS100110-13 9 DS100110-11 DS100110-12 www.national.com ...
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AC Timing Diagrams and Test Circuits FIGURE 12. Deserializer TRI-STATE Test Circuit and Timing FIGURE 13. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays www.national.com (Continued) DS100110-14 10 DS100110-15 ...
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AC Timing Diagrams and Test Circuits FIGURE 14. Deserializer PLL Lock Time from SyncPAT SW - Setup and Hold Time (Internal data sampling window Serializer Output Bit Position Jitter JIT t = Receiver Sampling Margin Time RSM FIGURE ...
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... I curve of CMOS designs. CC Powering Up the Serializer The DS92LV1021 must be powered up using a specific se- quence to properly start the PLL up. Not following the se- quence can cause the Bus LVDS outputs to be stuck in a certain output state. This may occur if the TCLK input is driven before power is applied to the Serializer ...
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Application Information (Continued) Noise Margin The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still reli- ably receive data. Various environmental and systematic fac- tors include: Serializer: TCLK jitter, V noise ...
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... Pin Diagrams www.national.com DS92LV1021TMSA - Serializer DS100110-18 DS92LV1210TMSA - Deserializer DS100110-19 14 ...
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Serializer Pin Description Pin Name I/O DIN I TCLK_R/F I DO+ O DO− O DEN I PWRDN I TCLK I SYNC I DVCC I DGND I AVCC I AGND I No. 3–12 Data Input. TTL levels inputs. Data on these ...
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Deserializer Pin Description Pin Name I/O ROUT O RCLK_R/F I RI+ I RI− I PWRDN I LOCK O RCLK O REN I DVCC I DGND I AVCC I AGND I REFCLK I www.national.com No. ± 15–19, Data Output ...
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Truth Table DIN (0–9) TCLK_R/F TCLK SYSTEM CLK L DATA 1 K DATA 0 RI RI− RCLK_R SYNC PTRN SYNC PTRN* X DATA (0–9) DATA (0–9)* ...
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... Physical Dimensions inches (millimeters) unless otherwise noted Order Number DS92LV1021TMSA or DS92LV1210TMSA LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or ...