DS92CK16 National Semiconductor, DS92CK16 Datasheet - Page 2
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DS92CK16
Manufacturer Part Number
DS92CK16
Description
3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver
Manufacturer
National Semiconductor
Datasheet
1.DS92CK16.pdf
(11 pages)
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CLKI/O+
CLKI/O−
OE
DE
CLK
CrdCLK
V
GND
V
GNDA
NC
Pin Name
Connection Diagram
TSSOP Package Pin Description
CC
CCA
OUT
IN
13, 15, 17, 19, 21,
1, 12, 14, 18, 22
16, 20, 24
Pin #
3, 10
5, 8
11
23
6
7
2
9
4
Ground
Ground
Power
Power
Type
I/O
I/O
See NS Package Number MTC24
O
Order Number DS92CK16TMTC
I
I
I
True (Positive) side of the differential clock input.
Complementary (Negative) side of the differential clock input.
OE; this pin is active Low. When High, this pin forces all CLK
pins High. When Low, CLK
either the CrdCLK
the logic level at the DE pin. This pin has a weak pullup device to
V
DE; this pin is active LOW. When Low, this pin enables the
CardCLK
the Driver is TRI-STATE
the state of the CLK
V
6 Buffered clock (CMOS) outputs.
Input clock from Card (CMOS level or TTL level).
V
or use separate power supplies). No special power sequencing
required. Either V
apply both power supplies.
GND
Analog V
separate power supplies). No special power sequencing required.
Either V
power supplies.
Analog Ground (Internally separate from Ground must be connected
externally).
No Connects
CC
CC
CC
. If OE is floating, then all CLK
. If DE is floating, then CLKI/O pins are TRI-STATE.
; Analog V
2
CCA
IN
CCA
signal to the CLKI/O pins and CLK
or V
(Internally separate from V
CCA
CC
CCA
IN
DS101082-2
(Internally separate from V
can be applied first, or simultaneously apply both
OUT
or the VID at the CLK/I/O pins with respect to
or V
®
pins. This pin has a weak pullup device to
, the CLKI/O pins are inputs and determine
CC
OUT
Description
can be applied first, or simultaneously
pins logic state is determined by
OUT
pins will be High.
CC
, connect externally or use
CC
OUT
, connect externally
pins. When High,
OUT