DS90CR484 National Semiconductor, DS90CR484 Datasheet - Page 5

• Manufacturer Part Number: DS90CR484
• Description: 48-Bit LVDS Channel Link Serializer/Deserializer
• Manufacturer: National Semiconductor

CLHT
CHLT
RCOP
RCOH
RCOL
RSRC
RHRC
RPDL
RPLLS
RPDD
RSKM
RDR
RDSS
Symbol
Over recommended operating supply and temperature ranges unless otherwise specified.
Receiver Switching Characteristics
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except V
Note 4: The Minimum and Maximum Limits are based on statistical analysis of the device performance over voltage and temperature ranges. This parameter is func-
tionally tested on Automatic Test Equipment (ATE). ATE is limited to 85MHz. A sample of characterization parts have been bench tested to verify functional perfor-
mance.
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output pulse positions
(min and max) and the receiver input setup and hold time (internal data sampling window - RSPOS). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable) and clock jitter.
RSKM
cable skew (type, length) + source clock jitter (cycle to cycle).
TH
CMOS/TTL Low-to-High Transition Time, ( Figure 3 ),
Rx data out
CMOS/TTL Low-to-High Transition Time, ( Figure 3 ),
Rx clock out
CMOS/TTL High-to-Low Transition Time, ( Figure 3 ),
Rx data out
CMOS/TTL High-to-Low Transition Time, ( Figure 3 ),
Rx clock out
RxCLK OUT Period, ( Figure 6 )
RxCLK OUT High Time, ( Figure
6 ), (Note 4)
RxCLK OUT Low Time, ( Figure 6 ),
(Note 4)
RxOUT Setup to RxCLK OUT,
( Figure 6 ), (Note 4)
RxOUT Hold to RxCLK OUT,
( Figure 6 ), (Note 4)
Receiver Propagation Delay - Latency, ( Figure 8 )
Receiver Phase Lock Loop Set ,( Figure 10 )
Receiver Powerdown Delay, ( Figure 12 )
Receiver Skew Margin without
Deskew, ( Figure 13 ), (Notes 4, 5)
Receiver Deskew Range
Receiver Deskew Step Size
, V
TL
, V
OD
and V
OD
).
CC
Parameter
= 3.3V and T
A
= +25˚C.
f = 112 MHz
f = 66 MHz
f = 112 MHz
f = 66 MHz
f = 112 MHz
f = 66 MHz
f = 112 MHz
f = 66 MHz
f = 112 MHz
f = 85 MHz
f = 66 MHz
f = 80 MHz
f = 80 MHz
5
3(TCIP)+4.0
(
±
±
8.928
Min
170
160
210
1TBIT)
1.786
3.5
6.0
3.5
6.0
2.4
3.6
3.4
7.0
(
3(TCIP)+4.8
±
0.3 TBIT
1.3 TBIT)
Typ
210
200
275
T
3(TCIP)+6.5
Max
30.3
2.0
1.0
2.0
1.0
10
1
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Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ps
ps
ps
ns
ns