DS2480 Dallas Semiconducotr, DS2480 Datasheet - Page 13

• Manufacturer Part Number: DS2480
• Description: Serial 1.Wire Line Driver
• Manufacturer: Dallas Semiconducotr

TIMING DIAGRAMS
This section explains the wave forms generated by the
DS2480 on the 1–Wire bus in detail. First the commu-
nication wave forms such as the Reset/Presence
Detect Sequence and the time slots are discussed.
After that follows a detailed description of the pulse
function under various conditions. The wave forms as
generated by the DS2480 may deviate slightly from
specifications found in the “Book of DS19xx iButton
Standards” or in data sheets of 1–Wire slave devices.
However, at a closer look one will find that all of the tim-
ing requirements are met.
1–WIRE COMMUNICATION WAVE FORMS
One of the major features of the DS2480 is that it
relieves the host from generating the timing of the
1–Wire signals and sampling the 1–Wire bus at the
appropriate times. How this is done for the reset/pres-
Reset/Presence Detect Figure 6a
After having received the command code for generating
a reset/presence sequence, the DS2480 pulls the
1–Wire bus low for t
The DS2480 will now wait for the short/interrupt sam-
pling offset t
1–Wire bus to determine if there is a short or an interrupt
signal. If there is no short or interrupt (as shown in the
picture), the DS2480 will wait for t
age on the 1–Wire bus for a presence pulse. Regardless
of the result of the presence test, the DS2480 will then
wait for t
response byte to the host.
Overdrive
Regular
Flexible
Speed
FILL
TESTING FOR SHORT AND/OR INTERRUPT
SI
5V
0V
to expire and then test the voltage on the
to expire and then send the command
RSTL
UNCONTROLLED
FALLING EDGE
512 s
512 s
and then lets it go back to 5V.
t
64 s
RSTL
t
RSTL
PDT
and test the volt-
RESET/PRESENCE SEQUENCE
t
SI
8 s
2 s
8 s
t
SI
ence detect sequence is shown in Figure 6a. This
sequence is composed of four timing segments: the
reset low time t
t
time t
prise the reset high time t
devices assert their presence or interrupt pulse. During
this time the DS2480 pulls the 1–Wire bus high with its
weak pull–up current.
The values of all timing segments for all 1–Wire speed
options are shown in the table. Since the reset/presence
sequence is slow compared to the time slots, the values
for regular and flexible speed are the same. Except for
the falling edge of the presence pulse all edges are con-
trolled by the DS2480. The shape of the uncontrolled
falling edge is determined by the capacitance of the
1–Wire bus and the number, speed and sink capability
of the slave devices connected.
If the test for interrupt or short reveals a logic 0, the
DS2480 will wait for 4096 s and then test the 1–Wire
bus again. If a logic 0 is detected, the 1–Wire bus is
shorted and a command response byte with the code for
SHORT will be sent immediately. If a logic 1 is detected,
the device will wait for t
send the command response byte with the code for an
alarming presence pulse. No additional testing for a
presence pulse will be done. The DS2480 will perform
the short/interrupt testing as described also at Over-
drive speed, although interrupt signaling is only defined
for regular speed.
SI
t
, the presence detect sampling offset t
PDT
64 s
64 s
PRESENCE
t
8 s
FILL
PDT
t
PULSE
RSTH
. The timing segments t
PRESENCE TESTING
RSTL
t
FILL
, the short/interrupt sampling offset
512 s
512 s
64 s
t
FILL
FILL
RSTH
to expire after which it will
TIME
IDLE
SI
where 1–Wire slave
, t
SLOT
TIME
PDT
PDT
and t
584 s
584 s
t
74 s
042498 13/26
RSTH
and a delay
FILL
DS2480
com-