DS2182A Dallas Semiconducotr, DS2182A Datasheet - Page 3

• Manufacturer Part Number: DS2182A
• Description: T1 Line Monitor
• Manufacturer: Dallas Semiconducotr

PIN DESCRIPTION Table 1
PIN
10
11
12
13
15
16
17
18
19
21
22
23
24
25
26
27
6
7
8
9
SYMBOL
RMSYNC
RCHCLK
RSIGSEL
RFSYNC
RABCD
ESIGFR
RLCLK
RLINK
RNEG
RCLK
RYEL
RSER
RPOS
RLOS
RFER
RBV
RCL
RST
NC
NC
TYPE
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
-
I
I
I
No Connect. No internal connection. This pin can be tied to either
V
Receive Yellow Alarm. Transitions high when yellow alarm
detected; goes low when alarm clears.
Receive Link Data. Updated with extracted FDL data one RCLK
before start of odd frames (193E) and held until next update.
Updated with extracted S-bit data one RCLK before start of even
frames (193S) and held until next update.
Receive Link Clock. 4 kHz demand clock for RLINK.
Receive Clock. 1.544 MHz primary clock.
Receive Channel Clock. 192 kHz clock; identifies time slot
(channel) boundaries.
Receive Serial Data. Received NRZ serial data; updated on rising
edges of RCLK.
No Connect. No internal connection. This pin can be tied to either
V
Receive Frame Sync. Extracted 8 kHz clock, one RCLK wide; F-
bit position in each frame.
Receive Multiframe Sync. Extracted multiframe sync; positive-
going edge indicates start of multiframe; 50% duty cycle.
Receive ABCD Signaling. Extracted signaling data output; valid
for each channel in signaling frames. In non-signaling frames,
RABCD outputs the LSB of each channel word.
Receive Signaling Frame. High during signaling frames; low
during non-signaling frames (and during resync).
Receive Signaling Select. In 193E framing, a .667 kHz clock that
identifies signaling frames A and C; a 1.33 kHz clock in 193S.
Reset. A high-low transition clears all internal registers and resets
counters. A high-low-high transition initiates a resync.
Receive Bipolar Data Inputs. Sampled on falling of RCLK. Tie
together to receive NRZ data and disable bipolar violation
monitoring circuitry.
Receive Carrier Loss. High if 192 consecutive 0s appear at RPOS
and RNEG; goes low upon seeing 12.5% one’s density.
Receive Bipolar Violation. High during accused bit time at RSER.
If bipolar violation detected, low otherwise.
Receive Frame Error. High during F-bit time when FT or FS
errors occur (193S), or when FPS or CRC errors occur (193E). Low
during resync.
Receive Loss of Sync. Indicates sync status; high when internal
resync is in progress, low otherwise.
SS
SS
or V
or V
DD
DD
, or it can be floated.
, or it can be floated.
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DESCRIPTION
DS2182A