DS2148 Dallas Semiconducotr, DS2148 Datasheet - Page 19

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DS2148

Manufacturer Part Number
DS2148
Description
5V E1/T1/J1 Line Interface
Manufacturer
Dallas Semiconducotr
Datasheet

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NOTES:
1) G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs require an
2) * Denotes active low.
ACRONYM
TRING
TNEG
TCLK
accuracy of ±32ppm for T1 interfaces.
TPOS
TEST
TTIP/
VSM
TX0/
TPD
TX1
V
V
DD
SS
PIN
34/
14/
21/
22/
43
26
13
41
37
15
36
20
35
42
I/O
O
I
I
I
I
I
I
-
I
-
DESCRIPTION
Transmit Clock. A 2.048 MHz or 1.544 MHz primary clock. Used
to clock data through the transmit side formatter.
3-State Control. Set high to 3-state all outputs and I/O pins
(including the parallel control port). Set low for normal operation.
Useful in board level testing.
Transmit Negative Data. Sampled on the falling edge (CES = 0) or
the rising edge (CES = 1) of TCLK for data to be transmitted out
onto the line.
Transmit Power-Down.
0 = normal transmitter operation
1 = powers down the transmitter and 3-states the TTIP and TRING
pins
Transmit Positive Data. Sampled on the falling edge (CES = 0) or
the rising edge (CES = 1) of TCLK for data to be transmitted out
onto the line.
Transmit Tip and Ring [TTIP & TRING]. Analog line driver
outputs. These pins connect via a step-up transformer to the line. See
Section 7 for details.
Transmit Data Source Select Bits 0 & 1 [H/W Mode]. These
inputs determine the source of the transmit data. See Table 4-6.
Positive Supply. 5.0V ±5%
Voltage Supply Mode. Should be tied high for 5V operation
Signal Ground.
19 of 75

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