LM3S102-IRN20(T) Luminary Micro, Inc., LM3S102-IRN20(T) Datasheet - Page 55

• Manufacturer Part Number: LM3S102-IRN20(T)
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Table 6-1. System Control Register Map (Sheet 2 of 2)
6.4
October 6, 2006
System Control
Offset
0x05C
0X144
0x044
0x048
0x050
0x054
0x058
0x060
0x064
0x100
0x104
0x108
0x110
0x114
0x118
0x120
0x124
0x128
0x150
0x160
Name
SRCR1
SRCR2
RIS
IMC
MISC
RESC
RCC
PLLCFG
RCGC0
RCGC1
RCGC2
SCGC0
SCGC1
SCGC2
DCGC0
DCGC1
DCGC2
DSLPCLKCFG
CLKVCLR
LDOARST
Register Descriptions
The remainder of this section lists and describes the System Control registers, in numerical order
by address offset.
0x07803AC0
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000001
0x00000000
0x00000000
0x00000001
0x00000000
0x00000000
0x00000001
0x00000000
0x00000000
0x07800000
0x00000000
0x00000000
Reset
-
-
R/W1C
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Preliminary
RO
RO
Description
Software Reset Control 1
Software Reset Control 2
Raw Interrupt Status
Interrupt Mask Control
Masked Interrupt Status and Clear
Reset Cause
Run-Mode Clock Configuration
XTAL to PLL translation
Run-Mode Clock Gating Control 0
Run-Mode Clock Gating Control 1
Run-Mode Clock Gating Control 2
Sleep-Mode Clock Gating Control 0
Sleep-Mode Clock Gating Control 1
Sleep-Mode Clock Gating Control 2
Deep-Sleep-Mode Clock Gating Control 0
Deep-Sleep-Mode Clock Gating Control 1
Deep-Sleep-Mode Clock Gating Control 2
Deep-Sleep Clock Configuration
Clock verification clear
Allow unregulated LDO to reset the part
LM3S102 Data Sheet
page
See
67
68
69
70
72
73
74
78
79
80
82
79
80
82
79
80
82
83
84
85
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