LM3553SD-NOPB National Semiconductor, LM3553SD-NOPB Datasheet - Page 9

• Manufacturer Part Number: LM3553SD-NOPB
• Description: 1.2A Dual Flash LED Driver System with I2C Compatible
• Manufacturer: National Semiconductor

Connection Diagram
I
DATA VALIDITY
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, the state of the data
line can only be changed when CLK is LOW.
A pull-up resistor between VIO and SDA must be greater than
[ (VIO-V
Using a larger pull-up resistor results in lower switching cur-
rent with slower edges, while using a smaller pull-up results
in higher switching currents with faster edges.
2
C Compatible Interface
OL
) / 3.7mA] to meet the V
FIGURE 1. Data Validity Diagram
Typical System Configuration
OL
ack = acknowledge (SDA pulled down by the slave)
requirement on SDA.
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id = chip address, 53h for LM3553
FIGURE 3. Write Cycle
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w = write (SDA = "0")
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START AND STOP CONDITIONS
START and STOP conditions classify the beginning and the
end of the I
signal transitioning from HIGH to LOW while SCL line is
HIGH. A STOP condition is defined as the SDA transitioning
from LOW to HIGH while SCL is HIGH. The I
generates START and STOP conditions. The I
sidered to be busy after a START condition and free after a
STOP condition. During data transmission, the I
can generate repeated START conditions. First START and
repeated START conditions are equivalent, function-wise.
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, the state of the data
line can only be changed when CLK is LOW.
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The master releases the SDA line (HIGH) during the acknowl-
edge clock pulse. The LM3553 pulls down the SDA line during
the 9th clock pulse, signifying an acknowledge. The LM3553
generates an acknowledge after each byte has been re-
ceived.
After the START condition, the I
dress. This address is seven bits long followed by an eighth
bit which is a data direction bit (R/W). The LM3553 address
is 53h. For the eighth bit, a “0” indicates a WRITE and a “1”
indicates a READ. The second byte selects the register to
which the data will be written. The third byte contains data to
write to the selected register.
FIGURE 2. Start and Stop Conditions
2
C session. A START condition is defined as SDA
2
C master sends a chip ad-
2
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C master always
2
C bus is con-
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2
C master
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