89C52 ATMEL Corporation, 89C52 Datasheet - Page 20

• Manufacturer Part Number: 89C52
• Description: Search ---> AT89C52
• Manufacturer: ATMEL Corporation

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Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for V
Shift Register Mode Timing Waveforms
AC Testing Input/Output Waveforms
Note:
4-80
Symbol
t
t
t
t
t
XLXL
QVXH
XHQX
XHDX
XHDV
V
CC
INSTRUCTION
- 0.5V
WRITE TO SBUF
0.45V
OUTPUT DATA
INPUT DATA
1.
CLEAR RI
CLOCK
AC Inputs during testing are driven at V
for a logic 1 and 0.45V for a logic 0. Timing mea-
surements are made at V
max. for a logic 0.
Parameter
Serial Port Clock Cycle Time
Output Data Setup to Clock Rising Edge
Output Data Hold After Clock Rising Edge
Input Data Hold After Clock Rising Edge
Clock Rising Edge to Input Data Valid
ALE
0.2 V
0.2 V
TEST POINTS
AT89C52
0
CC
CC
t
QVXH
+ 0.9V
- 0.1V
IH
min. for a logic 1 and V
CC
t
1
XHDV
= 5.0V
0
VALID
CC
20% and Load Capacitance = 80 pF.
2
- 0.5V
t
XLXL
t
1
XHQX
VALID
(1)
IL
3
Min
700
1.0
50
12 MHz Osc
0
t
XHDX
2
VALID
Float Waveforms
Note:
V
LOAD
4
Max
700
1.
3
VALID
V
V
For timing purposes, a port pin is no longer floating
when a 100 mV change from load voltage occurs. A
port pin begins to float when a 100 mV change from
the loaded V
LOAD
LOAD
5
10t
+ 0.1V
- 0.1V
2t
4
12t
CLCL
VALID
CLCL
Min
Variable Oscillator
CLCL
0
-117
OH
-133
Timing Reference
6
(1)
/V
5
OL
VALID
Points
level occurs.
10t
7
CLCL
Max
6
VALID
-133
SET TI
V
SET RI
V
OL
OL
8
- 0.1V
+ 0.1V
7
VALID
Units
ns
ns
ns
ns
s