87C575 Philips Semiconductors, 87C575 Datasheet - Page 24

• Manufacturer Part Number: 87C575
• Description: 80C51 8-bit microcontroller family 8K/256 OTP/ROM/ROMless/ 4 comparator/ failure detect circuitry/ watchdog timer
• Manufacturer: Philips Semiconductors

Philips Semiconductors
OSCILLATOR
CHARACTERISTICS
XTAL1 and XTAL2 are the input and output,
respectively, of an inverting amplifier. The
pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol,
page 4.
To drive the device from an external clock
source, XTAL1 should be driven while XTAL2
is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum
and maximum high and low times specified in
the data sheet must be observed.
Table 2. External Pin Status During Idle and Power-Down Modes
1998 May 01
Idle
Idle
Power-down
Power-down
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
MODE
PROGRAM MEMORY
External
External
Internal
Internal
IDLE MODE
In idle mode, the CPU puts itself to sleep
while all of the on-chip peripherals stay
active. The instruction to invoke the idle
mode is the last instruction executed in the
normal operating mode before the idle mode
is activated. The CPU contents, the on-chip
RAM, and all of the special function registers
remain intact during this mode. The idle
mode can be terminated either by any
enabled interrupt (at which time the process
is picked up at the interrupt service routine
and continued), or by a hardware reset which
starts the processor in the same manner as a
power-on reset.
ALE
1
1
0
0
24
PSEN
1
1
0
0
PORT 0
Float
Float
Data
Data
POWER-DOWN MODE
In the power-down mode, the oscillator is
stopped and the instruction to invoke
power-down is the last instruction executed.
Only the contents of the on-chip RAM are
preserved. The control bits for the reduced
power modes are in the special function
register PCON. Power-down mode can be
terminated with either a hardware reset or
external interrupt. With an external interrupt
INT0 or INT1 must be enabled and
configured as level sensitive. Holding the pin
low restarts to oscillator and bringing the pin
back high completes the exit.
If the watchdog is enabled (WDRUN = 1),
then power-down mode is disabled.
DESIGN CONSIDERATIONS
At power-on, the voltage on V
up with RST low for a proper start-up.
Table 2 shows the state of I/O ports during
low current operating modes.
PORT 1
Data
Data
Data
Data
80C575/83C575/
PORT 2
Address
Data
Data
Data
Product specification
87C575
CC
must come
PORT 3
Data
Data
Data
Data