87C51 Intel Corporation, 87C51 Datasheet
87C51
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87C51 Summary of contents
Page 1
... The Power Down mode saves the RAM contents but freezes the oscillator causing all other chip functions to be inoperative For the remainder of this document the 87C51 80C51BH and 80C31BH will be referred to as the 87C51 BH unless information applies to a specific device ...
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... MHz to 16 MHz MHz to 12 MHz MHz to 24 MHz Figure 1 87C51 BH Block Diagram 2 Table 1 Proliferation Options - - 272335 – 1 ...
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... PROCESS INFORMATION The 87C51 BH is manufactured on the CHMOS III-E process Additional process and reliability informa- tion is available in Intel’s Components Quality and Reliability Handbook Order No 210997 DIP Do not connect reserved pins 87C51 80C51BH 80C31BH PACKAGES Part Prefix 87C51 272335–2 ...
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... PIN DESCRIPTION V Supply voltage during normal Idle and Power CC Down operations V Circuit ground SS Port 0 Port 8-bit open drain bidirectional I O port As an output port each pin can sink several LS TTL inputs Port 0 pins that have 1’s written to them ...
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... ALE pulse is skipped during each access to external Data Memory PSEN Program Store Enable is the Read strobe to External Program Memory When the 87C51 BH is executing from Internal Program Memory PSEN is inactive (high) When the device is executing code from External Program Memory PSEN is activated ...
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... Down is the last instruction executed The on-chip RAM and Special Function Registers retain their val- ues until the Power Down mode is transmitted On the 87C51 BH either a hardware reset or an ex- ternal interrupt can cause an exit from Power Down Reset redefines all the SFR’s but does not change ...
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... ALE and PSEN are weakly pulled high The oscillator circuit remains ac- tive While the 87C51 this mode an emula- tor or test CPU can be used to drive the circuit Nor- mal operation is restored when a normal reset is ap- ...
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... ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias Storage Temperature Voltage Pin Voltage on Any Other Pin Maximum I per I O Pin OL Power Dissipation (Based on package heat transfer limitations not de- ...
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... RRST RST Pulldown Resistor C Pin Capacitance IO I Power Supply Current CC Active Mode 12 MHz (Figure 5) 16 MHz 24 MHz Idle Mode 12 MHz (Figure 5) 16 MHz 24 MHz Power Down Mode 87C51 80C51BH 80C31BH Min Typ(1) Max Unit ...
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... If I exceeds the test condition V may exceed the related specification OL OL Pins are not guaranteed to sink greater than the listed test conditions Figure 5 87C51 ALE and PSEN to momentarily fall below the for Power Down must be externally limited as follows ...
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... Test Condition Active Mode All other pins are disconnected CC 272335–8 Figure 7 I Test Condition Idle Mode CC All other pins are disconnected Figure 8 Clock Signal Waveform for I TCLCH 87C51 80C51BH 80C31BH 272335 –10 Figure 9 I Test Condition Power Down CC Mode All other pins are disconnected ...
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... Operating Conditions Load Capacitance for Port 0 ALE and PSEN 100 pF Load Capacitance for All Other Outputs e EXTERNAL MEMORY CHARACTERISTICS All parameter values apply to all devices unless otherwise indicated In this table 87C51 BH refers to 87C51 BH 87C51-1 BH-1 and 87C51-2 BH-2 Symbol Parameter 1 TCLCL Oscillator Frequency ...
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... EXTERNAL MEMORY CHARACTERISTICS All parameter values apply to all devices unless otherwise indicated In this table 87C51 BH refers to 87C51 BH 87C51-1 BH-1 and 87C51-2 BH-2 (Continued) Symbol Parameter TPXIX Input Instr Hold After PSEN TPXIZ Input Instr Float After PSEN 87C51 BH 87C51-24 BH-24 TAVIV Address to Valid Instr In ...
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... EXTERNAL MEMORY CHARACTERISTICS All parameter values apply to all devices unless otherwise indicated In this table 87C51 BH refers to 87C51 BH 87C51-1 BH-1 and 87C51-2 BH-2 (Continued) Symbol Parameter TWHQX Data Hold After WR 87C51 BH 87C51-24 BH-24 TQVWH Data Valid to WR High 87C51 BH 87C51-24 BH-24 TRLAZ RD Low to Address Float ...
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... EXTERNAL DATA MEMORY WRITE CYCLE EXTERNAL CLOCK DRIVE All parameter values apply to all devices unless otherwise indicated In this table 87C51 BH refers to 87C51 BH 87C51-1 BH-1 and 87C51-2 BH-2 Symbol Parameter 1 TCLCL Oscillator Frequency 87C51 BH 87C51-1 BH-1 87C51-2 BH-2 87C51-24 BH-24 TCHCX High Time 87C51 BH 8751-24 BH-24 TCLCX Low Time ...
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... SERIAL PORT TIMING SHIFT REGISTER MODE 12 MHz Symbol Parameter Oscillator Min TXLXL Serial Port Clock 1 0 Cycle Time TQVXH Output Data Setup 700 to Clock Rising Edge TXHQX Output Data Hold After Clock Rising Edge 87C51 BH 50 87C51-24 BH-24 TXHDX ...
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... PROGRAM SIGNALS ALE PROG ALE EA PSEN P2 6 PROG 75V 75V 75V 75V 75V 87C51 80C51BH 80C31BH ...
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... The encryption array is not available without the lock bit For the lock bit to be programmed the user must submit an encryp- tion table The 87C51 has a 3-level program lock system and a 64-byte encryption array Since this is an EPROM device all locations are user-program- ...
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... Program Lock Bits The 87C51 has 3 programmable lock bits that when programmed according to Table 5 will provide differ- ent levels of protection for the on-chip code and data Erasing the EPROM also erases the encryption ar- ray and the program lock bits returning the part to ...
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... EPROM PROGRAMMING EPROM AND ROM VERIFICATION CHARACTERISTICS ( 10 Symbol Parameter V Programming Supply Voltage PP I Programming Supply Current PP 1 TCLCL Oscillator Frequency TAVGL Address Setup to PROG Low TGHAX Address Hold After PROG TDVGL ...
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... Added P3 3 control pin to programming and veri- fication 7 Added 80C51BH signature byte Device The following differences exist between the ‘‘-002’’ 87C51 and the ‘‘-001’’ version of the 87C51 80C51BH BH 80C31BH datasheet 87C51 BH 1 Removed ...