87C196LA Intel Corporation, 87C196LA Datasheet - Page 13

• Manufacturer Part Number: 87C196LA
• Description: CHMOS 16-BIT MICROCONTROLLER
• Manufacturer: Intel Corporation

T2CLK
T2DIR
TXD
V
V
V
V
WR#
PRODUCT PREVIEW
CC
PP
REF
SS
, V
Name
SS
1
Type
PWR
PWR
PWR
GND
O
O
I
I
Timer 2 External Clock
External clock for timer 2. Timer 2 increments (or decrements) on both rising
and falling edges of T2CLK. It is also used in conjunction with T2DIR for
quadrature counting mode.
T2CLK shares a package pin with P1.0 and EPA0.
Timer 2 External Direction
External direction (up/down) for timer 2. Timer 2 increments when T2DIR is high
and decrements when it is low. It is also used in conjunction with T2CLK for
quadrature counting mode.
T2DIR shares a package pin with P1.2 and EPA2.
Transmit Serial Data
In serial I/O modes 1, 2, and 3, TXD transmits serial port output data. In mode
0, it is the serial clock output.
TXD shares a package pin with P2.0 and PVER.
Digital Supply Voltage
Connect each V
Programming Voltage
V
50 ns. Use this method to exit powerdown only when using an external clock
source because it enables the internal phase clocks, but not the internal
oscillator.
If you do not plan to use the powerdown feature, connect V
Reference Voltage for the A/D Converter
This pin supplies operating voltage to the A/D converter.
Digital Circuit Ground
These pins supply ground for the digital circuitry. Connect each V
to ground through the lowest possible impedance path. V
to the core ground region of the microcontroller, while V
to the port ground region. (ANGND is connected to the analog ground region.)
Separating the ground regions provides noise isolation.
Write
This active-low output indicates that an external write is occurring. This signal is
asserted only during external memory writes.
Forcing WR# high while RESET# is low causes the device to enter PLL-bypass
mode. When the device is in PLL-bypass mode, the internal phase clocks
operate at one-half the frequency of the frequency on XTAL1.
WR# shares a package pin with P5.2, WRL#, and PLLEN.
†
PP
When this pin is configured as a special-function signal (P5_MODE.2 = 1), the
chip configuration register 0 (CCR0) determines whether it functions as WR#
or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
causes the device to exit powerdown mode when it is driven low for at least
Table 4. Signal Descriptions (Continued)
†
CC
pin to the digital supply voltage.
Description
AUTOMOTIVE — 87C196LA
SS
SS
1
PP
pins are connected
pins are connected
to V
SS
CC
and V
.
SS
1
pin
13