83C453 Philips Semiconductors, 83C453 Datasheet
83C453
Related parts for 83C453
83C453 Summary of contents
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... OTP/ROM, expanded I/O Preliminary specification Supersedes data of 1997 Dec 29 IC20 Data Handbook INTEGRATED CIRCUITS 1998 Apr 23 ...
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... Normal operation: less than 24mA at 5V, 16MHz – Idle mode – Power-down mode Reduced EMI Full-duplex enhanced UART – Framing error detection – Automatic address recognition TEMPERATURE C AND PACKAGE 68–Pin Plastic Leaded Chip Carrier +70 2 Preliminary specification 83C453/87C453 FREQ. PKG. DWG (MHz SOT188-3 ...
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... DPL CSR SBUF IE PSW INTERRUPT, SERIAL PORT AND TIMER BLOCKS PORT 6 LATCH PORT 6 PORT 6 CONTROL/STATUS DRIVERS P6.0–P6.7 IDS ODS BFLAG AFLAG 3 Preliminary specification 83C453/87C453 P5.0–5.7 PORT 5 DRIVERS PORT 5 EPROM LATCH PROGRAM ADDRESS REGISTER BUFFER TCON TH1 AUXR PC IP INCRE- MENTER ...
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... ADDRESS BUS 5 P2.3/A11 6 P2.4/A12 7 P2.5/A13 8 P2.6/A14 9 P2.7/A15 10 P0.7/AD7 11 P0.6/AD6 12 P0.5/AD5 13 P0.4/AD4 14 P0.3/AD3 15 P0.2/AD2 16 P0.1/AD1 17 P0.0/AD0 P4.7 20 P4.6 21 P4.5 SU00085 22 P4.4 23 P4.3 4 Preliminary specification 83C453/87C453 LCC Pin Function Pin Function 24 P4.2 47 P5.3 25 P4.1 48 P5.4 26 P4.0 49 P5.5 27 P1.0 50 P5.6 28 P1.1 51 P5.7 29 P1.2 52 XTAL2 30 P1.3 53 XTAL1 31 P1.4 54 ...
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... Crystal 1: Input to the inverting oscillator amplifier that forms the oscillator. This input receives the external oscillator when an external oscillator is used. XTAL2 52 O Crystal 2: An output of the inverting amplifier that forms the oscillator. This pin should be floated when an external oscillator is used. 1998 Apr 23 83C453/87C453 ) during EPROM programming Preliminary specification . CC ...
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... RS0 SM0 SM1 SM2 REN TB8 TF1 TR1 TF0 TR0 IE1 GATE C GATE 6 Preliminary specification 83C453/87C453 RESET LSB VALUE 00H 00H IDSM OBF IBF FCH 00H 00H PX1 PT0 PX0 x0000000B – ...
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... Enables or disables External Interrupt 0. If EX0=0, external Interrupt 0 is disabled. 1998 Apr 23 IE REGISTER IP REGISTER GLOBAL DISABLE Figure 1. 8XC453 Interrupt Control System IIB ES ET1 EX1 Figure 2. 8XC453 Interrupt Enable (IE) Register 7 Preliminary specification 83C453/87C453 HIGH PRIORITY INTERRUPT INTERRUPT POLLING SEQUENCE LOW PRIORITY INTERRUPT SU00562 LSB ET0 EX0 SU00563 ...
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... Apr 23 PIB PS PT1 PX1 Figure 3. 8XC453 Interrupt Priority (IP) Register — POF GF1 GF0 . If then cleared by software, it can be used to determine CC Figure 4. Power Control Register (PCON) VECTOR ADDRESS 8 Preliminary specification 83C453/87C453 LSB PT0 PX0 SU00564 IDL SU00565 ...
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... SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR) SM0 TO UART MODE CONTROL SM1 SM2 REN TB8 RB8 – POF LVF GF0 Figure 6. UART Framing Error Detection 9 Preliminary specification 83C453/87C453 Reset Value = 0000 0000B SU00043 D7 D8 ONLY IN STOP MODE 2, 3 BIT SCON ...
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... In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = SADEN = Given Slave 1 SADDR = SADEN = Given Slave 2 SADDR = SADEN = Given 10 Preliminary specification 83C453/87C453 D8 SCON RB8 TI RI (98H) SU00045 1100 0000 1111 1101 = 1100 00X0 1100 0000 1111 1110 = 1100 000X ...
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... On the 87C453 either a hardware reset or external interrupt can cause an exit from Power Down. Reset redefines all the SFRs but 1998 Apr 23 83C453/87C453 does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. ...
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... IDS pin sets the IBF flag. Port 6 input buffer is transparent when IDS is low, and latched when IDS is high. 1998 Apr 23 83C453/87C453 CSR.3 Output Buffer Full Flag Clear Mode (OBFC) – When CSR the positive edge of the ODS input clears the OBF flag. ...
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... DF DE CSR SADEN B9 AUXR 8E Bit 4 Bit 3 MA0 OBFC Output Buffer Flag Clear Mode 0 = Negative edge of ODS 1 = Positive edge o ODS 13 Preliminary specification 83C453/87C453 IDS IDS MODE EDGE/LEVEL SELECT (CSR.2) SU00087 BIT ADDRESS LSB ...
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... IL IH See note ALE and the other ports. The noise is due OL on ALE and PSEN to momentarily fall below the 0.9V OH MAX is given in mA. See Figure 20 Preliminary specification 83C453/87C453 RATING UNIT 0 to +70 C –65 to +150 C –0.5 to +6.5 V 1.5 W unless otherwise noted. ...
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... IDS width ILIH t 15 Data setup to IDS high or PE high DVIH t 15 Data hold after IDS high or PE high IHDZ t 16 IDS to BFLAG (IBF) delay IVFV 1998 Apr 23 83C453/87C453 16MHz CLOCK VARIABLE CLOCK MIN MAX MIN 3 –40 CLCL 22 t –40 CLCL ...
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... Fall time CHCL NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 1998 Apr 23 83C453/87C453 16MHz CLOCK VARIABLE CLOCK MIN MAX MIN 209 3t ...
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... RHDX DATA IN t AVDV P2.0–P2.7 OR A8–A15 FROM DPH Figure 10. External Data Memory Read Cycle 17 Preliminary specification 83C453/87C453 = Time for address valid to ALE low. = Time for ALE low to PSEN low. A0–A7 A8–A15 SU00056 A0–A7 FROM PCL INSTR IN A0–A15 FROM PCH ...
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... Figure 11. External Data Memory Write Cycle XHQX XHDX VALID VALID VALID Figure 12. Shift Register Mode Timing 18 Preliminary specification 83C453/87C453 A0–A7 FROM PCL INSTR IN A0–A15 FROM PCH SU00008 SET TI VALID VALID VALID VALID SET RI ...
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... Apr 23 t OVFV t OLOH t OLDV t FLDV Figure 13. Port 6 Output t OHFH t t FVDV FVDV CSR Figure 14. Port 6 Select Mode t FLFH t ILIH t DVIH Figure 15. Port 6 Input t IVFV Figure 16. IBF Flag Output 19 Preliminary specification 83C453/87C453 t OVFV t OHDZ SU00088 DATA SU00089 t IHDZ SU00090 t IVFV SU00091A ...
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... MAX ACTIVE MODE TYP ACTIVE MODE 10 5 MAX IDLE MODE TYP IDLE MODE 4MHz 8MHz 12MHz 16MHz FREQ AT XTAL1 Figure 20. I vs. FREQ CC 20 Preliminary specification 83C453/87C453 SU00009 +0.1V V –0.1V TIMING OH REFERENCE POINTS –0.1V V +0. 20mA SU00718 Figure 19. Float Waveform SU00092 ...
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... (NC) XTAL2 V CC XTAL1 V SS IDS ODS SU00095 Test Condition, Power Down Mode CC All other pins are disconnected 5. Preliminary specification 83C453/87C453 RST XTAL2 V CC XTAL1 V SS IDS ODS SU00094 Test Condition, Idle Mode ...
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... ALE/PROG EA/V P2 held at 12.75V. Each programming pulse is low for 100 and high PP 22 Preliminary specification 83C453/87C453 2 rating P2.6 P3.7 P3 ...
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... MIN Figure 26. PROG Waveform + RST EA/V PP P3.6 ALE/PROG 87C453 P3.7 PSEN XTAL2 P2.7 P2.6 XTAL1 P2.0–P2 Figure 27. Program Verification 23 Preliminary specification 83C453/87C453 PGM DATA +12.75V 100 s PULSES TO GROUND A8–A12 SU00159 100 s+10 SU00160 PGM DATA ENABLE 0 A8–A12 SU00161 ...
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... FOR VERIFICATION CONDITIONS SEE FIGURE 27. 1998 Apr 23 * ADDRESS DATA IN t GHDX t GHAX t GHGL t GHSL LOGIC 1 LOGIC 0 t ELQV Figure 28. EPROM Programming and Verification 24 Preliminary specification 83C453/87C453 MIN MAX UNIT 12.5 13 MHz 48t CLCL 48t CLCL 48t CLCL 48t CLCL 48t ...
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... Philips Semiconductors 80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O PLCC68: plastic leaded chip carrier; 68 leads; pedestal 1998 Apr 23 83C453/87C453 25 Preliminary specification SOT188-3 ...
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... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 1998 Apr 23 [1] Copyright Philips Electronics North America Corporation 1998 Document order number: 26 Preliminary specification 83C453/87C453 All rights reserved. Printed in U.S.A. Date of release: 05-98 9397 750 03886 ...