83C196LC Intel Corporation, 83C196LC Datasheet

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83C196LC

Manufacturer Part Number
83C196LC
Description
CHMOS 16-BIT MICROCONTROLLER
Manufacturer
Intel Corporation
Datasheet
The 83C196LC, 83C196LD are low-cost, pin-compatible replacements for the existing 87C196JT and
87C196JR, respectively. These products feature an enhanced synchronous serial I/O (SSIO) port for more
flexible communication to other devices. The enhanced SSIO is compatible with Motorola’s Serial Peripheral
Interface (SPI) protocol and National’s Microwire protocol. To optimize die size, the A/D converter was
removed for use in those applications that use an off-chip A/D converter.
The MCS
The 83C196LC, 83C196LD are composed of a high-speed core with the following peripherals: an
asynchronous/synchronous serial I/O port (8096 compatible) with a dedicated 16-bit baud-rate generator; an
additional synchronous serial I/O port with full duplex master/slave transceivers; a flexible timer/counter
structure with prescaler, cascading, and quadrature capabilities; six modularized, multiplexed high-speed I/O
for capture and compare (called event processor array) with 200 ns resolution and double buffered inputs;
and a sophisticated, prioritized interrupt structure with programmable peripheral transaction server (PTS).
The 83C196LC has the highest memory density of the 52-pin MCS 96 microcontroller family, with 32 Kbytes
of on-chip ROM, 1 Kbyte of on-chip register RAM, and 512 bytes of code RAM. The high memory integration
of the 83C196LC supports high functionality in a low pin-count package and the use of the C programming
language.
COPYRIGHT © INTEL CORPORATION, 1996
12 MHz standard; 18 MHz and 22 MHz are speed
premium
22 MHz operation
32 Kbytes of on-chip ROM (LC)
16 Kbytes of on-chip ROM (LD)
1 Kbyte of on-chip register RAM (LC)
384 bytes of on-chip register RAM (LD)
512 bytes of on-chip code RAM
(LC only)
Register-to-register architecture
Peripheral transaction server (PTS)
with high-speed, microcoded interrupt
service routines
Full-duplex serial I/O port with
dedicated baud-rate generator
Enhanced full-duplex, synchronous
serial I/O port (SSIO)
®
This document contains information on products in the sampling and initial production
phases of development. The specifications are subject to change without notice. Verify
with your local Intel sales office that you have the latest datasheet before finalizing a
design.
96 microcontroller family members are all high-performance microcontrollers with 16-bit CPUs.
CHMOS 16-BIT MICROCONTROLLER
83C196LC, 83C196LD
Automotive
December 1996
NOTE
High-speed event processor array
— Six capture/compare channels
— Two compare-only channels
— Two 16-bit software timers
Programmable 8- or 16-bit external bus
Design enhancements for EMI
reduction
Oscillator failure detection circuitry
SFR register that indicates the source
of the last reset
Watchdog timer (WDT)
Cost reduced replacements for the
87C196JT and 87C196JR.
–40° C to +125° C ambient temperature
52-pin PLCC package
ADVANCE INFORMATION
Order Number: 272805-001

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83C196LC Summary of contents

Page 1

... The 83C196LC has the highest memory density of the 52-pin MCS 96 microcontroller family, with 32 Kbytes of on-chip ROM, 1 Kbyte of on-chip register RAM, and 512 bytes of code RAM. The high memory integration of the 83C196LC supports high functionality in a low pin-count package and the use of the C programming language. ...

Page 2

... Microcode Engine Source (16) Register RAM Memory 1 Kbyte (LC) Interface ALU 384 Bytes (LD) Destination (16) † A seventh capture/compare channel (EPA7) is available as a software timer not connected to a package pin. Figure 1. 83C196LC, 83C196LD Block Diagram 2 Port 6 Port 0 Enhanced SSIO Peripheral Transaction Server Interrupt Controller ...

Page 3

... XX Table 1. Description of Product Nomenclature Parameter Temperature and Burn-in Options Packaging Options Program-memory Options Process Information Product Family Device Speed ADVANCE INFORMATION AUTOMOTIVE — 83C196LC, 83C196LD XXXXX XX Figure 2. Product Nomenclature Options A Automotive operating temperature range (–40° 125° C ambient) with Intel standard burn-in. ...

Page 4

... AUTOMOTIVE 2.0 PINOUT AD14 / P4.6 AD13 / P4.5 AD12 / P4.4 AD11 / P4.3 AD10 / P4.2 AD9 / P4.1 AD8 / P4.0 AD7 / P3.7 AD6 / P3.6 AD5 / P3.5 AD4 / P3.4 AD3 / P3.3 AD2 / P3.2 Figure 3. 83C196LC, 83C196LD 52-pin PLCC Package Table 2. 83C196LC, 83C196LD 52-pin PLCC Package Pin Assignments Pin Name Pin P5.0/ADV#/ALE ...

Page 5

... AD12 10 P3.2 AD13 9 P3.3 AD14 8 P3.4 AD15 7 P3.5 P3.6 Input P3.7 Name Pin P4.0 P0.2 33 P4.1 P0.3 34 P4.2 P0.4 35 P4.3 P0.5 36 P4.4 P0.6 37 P4.5 P0.7 38 P4.6 ADVANCE INFORMATION AUTOMOTIVE — 83C196LC, 83C196LD Input/Output (Cont’d) Pin Name Pin P6.0/EPA8 45 28 P6.1/EPA9 46 29 P6.4/SC0 47 30 P6.5/SD0 48 31 P6.6/SC1 49 32 P6.7/SD1 Power & Ground ...

Page 6

... AUTOMOTIVE 3.0 SIGNALS Name Type AD15:0 I/O Address/Data Lines These pins provide a multiplexed address and data bus. During the address phase of the bus cycle, address bits 0–15 are presented on the bus and can be latched using ALE or ADV#. During the data phase 16-bit data is transferred ...

Page 7

... This is a memory-mapped, 8-bit, bidirectional port with programmable open- drain or complementary output modes. The pins are shared with the multiplexed address/data bus, which has complementary drivers. P3.7:0 share package pins with AD7:0. ADVANCE INFORMATION AUTOMOTIVE — 83C196LC, 83C196LD Description specification to prevent IH IH ...

Page 8

... AUTOMOTIVE Table 4. Signal Descriptions (Continued) Name Type P4.7:0 I/0 Port 4 This is a memory-mapped, 8-bit, bidirectional port with open-drain or complementary output modes. The pins are shared with the multiplexed address/data bus, which has complementary drivers. P4.7:0 share package pins with AD15:8. P5.3:2 I/O Port 5 P5 ...

Page 9

... WRL# shares a package pin with P5.2 and WR#. † When this pin is configured as a special-function signal (P5_MODE.2 = 1), the chip configuration register 0 (CCR0) determines whether it functions as WR# or WRL#. CCR0 selects WR#; CCR0 selects WRL#. ADVANCE INFORMATION AUTOMOTIVE — 83C196LC, 83C196LD Description pin to the digital supply voltage. CC † ...

Page 10

... AUTOMOTIVE Table 4. Signal Descriptions (Continued) Name Type XTAL1 I Input Crystal/Resonator or External Clock Input Input to the on-chip oscillator and the internal clock generators. The internal clock generators provide the peripheral clocks, CPU clock, and CLKOUT signal. When using an external clock source instead of the on-chip oscillator, connect the clock input to XTAL1 ...

Page 11

... (Oscillator frequency)....................... 4 MHz to 22 MHz 1 XTAL ADVANCE INFORMATION AUTOMOTIVE — 83C196LC, 83C196LD Table 5. Address Map Description NOTICE: This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design ...

Page 12

... AUTOMOTIVE 5.1 DC Characteristics Table 6. DC Characteristics at V Symbol Parameter I V supply current 40° +125° C – ambient) I Active mode supply cur rent (typical) I Idle mode current IDLE I Powerdown mode PD current V Input low voltage IL (all pins) V Input high voltage (all ...

Page 13

... Target values OL OH are ± 10 mA. 6. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and V = 5.0V. CC ADVANCE INFORMATION AUTOMOTIVE — 83C196LC, 83C196LD = 4.5V – 5.5V (Continued) CC Min Typical Max Units 10 pF 150K ...

Page 14

... AUTOMOTIVE 5.2 AC Characteristics Test Conditions: capacitive load on all pins = 100 pF, rise and fall times = 10 ns, F Symbol Parameter The 83C196LC, 83C196LD meets these specifications F Oscillator Frequency 1 XTAL T Oscillator Period (1/F 1 XTAL XTAL T XTAL1 High to CLKOUT High or Low XHCH T CLKOUT Cycle Time ...

Page 15

... AD15:0, AD7:0 L ALE Q AD15:0, AD7:0 R RD# W WR#, WRL# Character H High L Low V Valid X No Longer Valid Z Floating (low impedance) ADVANCE INFORMATION AUTOMOTIVE — 83C196LC, 83C196LD Min Max 3 T – XTAL T – XTAL T – XTAL T 1 XTAL 0 Signal(s) Condition Units ...

Page 16

... AUTOMOTIVE XTAL1 CLKOUT T CLLH ALE/ADV# T LHLL RD# T AVLL Address Out AD15:0 (read) T AVDV WR# AD15:0 Address Out (write) AD15:8 (8-bit data bus XTAL1 CLCL CHCL XHCH T LLCH T LHLH T T RHLH T LLRL RLRH T T RHDZ RLAZ T T RLDV ...

Page 17

... T XLXL TXD x T QVXH RXD (Out) T DVXH RXD x Valid Valid (In) Figure 5. Serial Port Waveform — Shift Register Mode ADVANCE INFORMATION AUTOMOTIVE — 83C196LC, 83C196LD = 5.0V ± 10 0.0V; Load Capacitance = 100 Min XTAL 4 T – XTAL XTAL 2 T – 50 ...

Page 18

... AUTOMOTIVE 5.4 AC Characteristics — Synchronous Serial Port Table 10. Synchronous Serial Port Timing Symbol Parameter T Synchronous Serial Port Clock period CLCL T Synchronous Serial Port Clock falling edge to CLCH rising edge T Setup time for MSB output Setup time for D6:0 output ...

Page 19

... XLXL T High Time XHXX T Low Time XLXX T Rise Time XLXH T Fall Time XHXL T XHXX 0 0 XTAL1 Figure 7. External Clock Drive Waveforms ADVANCE INFORMATION AUTOMOTIVE — 83C196LC, 83C196LD Table 11. External Clock Drive Min 4.0 ) 45.45 1 XTAL 0. XTAL 0. XTAL T XLXH 0 XLXX 0.3 V – 0.5 V ...

Page 20

... AUTOMOTIVE 5.6 Test Output Waveforms 3.5 V 0.45 V Note: AC testing inputs are driven at 3.5 V for a logic “1” and 0.45 V for a logic “0”. Timing measurements are made at 2.0 V for a logic “1” and 0.8 V for a logic “0”. Figure 8. AC Testing Input, Output Waveforms ...

Page 21

... Write cycle during reset. If the microcontroller is reset during a write cycle, the contents of the external memory device may be corrupted. • EPA7. This function exists in the83C196LC and LD, but the associated pin is omitted. You can use this channel either as a software timer or to reset the timers. ...

Page 22

... AUTOMOTIVE • I/O port pins. The following port pins do not exist in the 83C196LC and LD: P0.0–P0.1, P1.4–P1.7, P2.3 and P2.5, P5.1 and P5.4–P5.7, P6.2 and P6.3. Software can still read and write the associated Px_REG, Px_MODE, and Px_DIR registers. Configure the registers for the removed pins as follows: — ...

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