83C166 Siemens Semiconductor Group, 83C166 Datasheet
83C166
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83C166 Summary of contents
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... Microcomputer Components 16-Bit CMOS Single-Chip Microcontroller SAB 80C166/83C166 Data Sheet 09.94 ...
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... Single-Cycle Context Switching Support Up to 256 KBytes Linear Address Space for Code and Data 1 KByte On-Chip RAM 32 KBytes On-Chip ROM (SAB 83C166 only) Programmable External Bus Characteristics for Different Address Ranges 8-Bit or 16-Bit External Data Bus Multiplexed or Demultiplexed External Address/Data Buses ...
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... Figure 1 Logic Symbol Ordering Information Type Ordering Code Package SAB 83C166-5M Q67121-D... SAB 83C166-5M-T3 Q67121-D... SAB 80C166-M Q67121-C848 SAB 80C166-M-T3 Q67121-C900 Note: The ordering codes (Q67120-D...) for the Mask-ROM versions are defined for each product after verification of the respective ROM code. ...
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... Pin Configuration Rectangular P-MQFP-100-2 (top view) Figure 2 Semiconductor Group SAB 80C166 3 SAB 80C166/83C166 ...
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... SAB 80C166. An internal pullup resistor permits power-on reset using only a capacitor connected to Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. 4 SAB 80C166/83C166 ...
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... The following Port 2 pins also serve for alternate functions: P2.0 CC0IO CAPCOM: CC0 Cap.-In/Comp.Out ... ... ... P2.13 CC13IO CAPCOM: CC13 Cap.-In/Comp.Out, BREQ External Bus Request Output P2.14 CC14IO CAPCOM: CC14 Cap.-In/Comp.Out, HLDA External Bus Hold Acknowl. Output P2.15 CC15IO CAPCOM: CC15 Cap.-In/Comp.Out, HOLD External Bus Hold Request Input 5 SAB 80C166/83C166 ...
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... Data Path Width: 8-bit P0.0 – P0.7: D0 – D7 P0.8 – P0.15: output! Multiplexed bus modes: Data Path Width: 8-bit P0.0 – P0.7: AD0 – AD7 P0.8 – P0.15 A15 Reference voltage for the A/D converter. Reference ground for the A/D converter. 6 SAB 80C166/83C166 16-bit D15 16-bit AD0 - AD7 AD8 - AD15 ...
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... Pin Definitions and Functions (cont’d) Symbol Pin Input Number Output 38, 61 39, 60, 78, 94 Semiconductor Group Function Digital Supply Voltage during normal operation and idle mode. 2.5 V during power down mode Digital Ground. 7 SAB 80C166/83C166 ...
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... The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the SAB 80C166. Note: All time specifications refer to a CPU clock of 20 MHz (see definition in the AC Characteristics section). Figure 3 Block Diagram Semiconductor Group SAB 80C166/83C166 8 ...
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... The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. The SAB 83C166 contains 32 KBytes of on-chip mask-programmable ROM for code or constant data. The ROM can be mapped to either segment 0 or segment 1. ...
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... CPU at a time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. 32 KByte in the SAB 83C166 Figure 4 CPU Block Diagram Semiconductor Group 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 SAB 80C166/83C166 1 KByte ...
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... Return Instructions – System Control Instructions – Miscellaneous Instructions The basic instruction length is either bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands. Semiconductor Group SAB 80C166/83C166 11 ...
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... Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individual trap (interrupt) number. The following table shows all of the possible SAB 80C166 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Semiconductor Group SAB 80C166/83C166 12 ...
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... T4IE T5IR T5IE T6IR T6IE CRIR CRIE ADCIE ADEIR ADEIE S0TIR S0TIE S0RIR S0RIE S0EIR S0EIE S1TIR S1TIE S1RIR S1RIE S1EIR S1EIE 13 SAB 80C166/83C166 Interrupt Vector Vector Location CC0INT 40 H CC1INT 44 H CC2INT 48 H CC3INT 4C H CC4INT 50 H CC5INT 54 H CC6INT ...
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... STKUF STUTRAP 0018 UNDOPC BTRAP 0028 PRTFLT BTRAP 0028 ILLOPA BTRAP 0028 ILLINA BTRAP 0028 ILLBUS BTRAP 0028 [002C 003C Any [0000 01FC in steps SAB 80C166/83C166 Trap Trap Number Priority 00 III III III ...
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... Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow; only one compare event per timer period is generated Double Two registers operate on one pin; pin toggles on each compare match; Register Mode several compare events per timer period are possible. Semiconductor Group SAB 80C166/83C166 15 ...
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... Figure 5 CAPCOM Unit Block Diagram Semiconductor Group SAB 80C166/83C166 16 ...
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... For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 400 MHz CPU clock). Figure 6 Block Diagram of GPT1 Semiconductor Group SAB 80C166/83C166 17 ...
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... T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. Figure 7 Block Diagram of GPT2 Semiconductor Group SAB 80C166/83C166 18 ...
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... Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and converted. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. Semiconductor Group SAB 80C166/83C166 19 ...
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... Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. Semiconductor Group SAB 80C166/83C166 20 ...
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... RAM. To execute the loaded code the BSL then jumps to location 0FA40 loaded program may load additional code / data, change modes, etc. The SAB 80C166 exits BSL mode upon a software reset (ignores the ALE level hardware reset (remove conditions for entering BSL mode before). Semiconductor Group SAB 80C166/83C166 > through 0FA5F ...
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... Compare word data to GPR and increment GPR by 1/2 Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR Shift left/right direct word GPR Rotate left/right direct word GPR Arithmetic (sign bit) shift right direct word GPR 22 SAB 80C166/83C166 Bytes ...
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... Return from interrupt service subroutine Software Reset Enter Idle Mode Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Null operation 23 SAB 80C166/83C166 Bytes ...
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... CAPCOM Register 3 Interrupt Control Register H CAPCOM Register 4 H CAPCOM Register 4 Interrupt Control Register H CAPCOM Register 5 H CAPCOM Register 5 Interrupt Control Register H CAPCOM Register 6 H CAPCOM Register 6 Interrupt Control Register H CAPCOM Register SAB 80C166/83C166 Reset Value 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H ...
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... CPU Code Segment Pointer Register H (2 bits, read only) Port 0 Direction Control Register H Port 1 Direction Control Register H Port 2 Direction Control Register H Port 3 Direction Control Register H Port 4 Direction Control Register (2 bits SAB 80C166/83C166 Reset Value 0000 H 0000 H 0000 H 0000 H 0000 H 0000 ...
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... PEC Channel 7 Control Register H CPU Program Status Word H Serial Channel 0 Baud Rate Generator Reload H Register Serial Channel 0 Control Register H Serial Channel 0 Error Interrupt Control Register H Serial Channel 0 Receive Buffer Register H (read only) 26 SAB 80C166/83C166 Reset Value 0000 H 0001 H 0002 H 0003 H 0000 H 0000 H ...
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... CAPCOM Timer 0 Interrupt Control Register H CAPCOM Timer 0 Reload Register H CAPCOM Timer 1 Register H CAPCOM Timer 1 Interrupt Control Register H CAPCOM Timer 1 Reload Register H GPT1 Timer 2 Register H GPT1 Timer 2 Control Register H GPT1 Timer 2 Interrupt Control Register H 27 SAB 80C166/83C166 Reset Value 0000 0000 H 0000 H 0000 H 0000 ...
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... GPT2 Timer 6 Register H GPT2 Timer 6 Control Register H GPT2 Timer 6 Interrupt Control Register H Trap Flag Register H Watchdog Timer Register (read only) H Watchdog Timer Control Register H Constant Value 0’s Register (read only SAB 80C166/83C166 Reset Value 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H ...
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... Absolute Maximum Ratings Ambient temperature under bias ( SAB 83C166-5M, SAB 80C166-M.................................................................................. ˚C SAB 83C166-5M-T3, SAB 80C166-M-T3 .................................................................. – ˚C T Storage temperature ( ) ....................................................................................... – 150 ˚C ST Voltage on V pins with respect to ground ( CC Voltage on any pin with respect to ground ( Input current on any pin during overload condition.................................................. – Absolute sum of all input currents during overload condition ...
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... DC Characteristics +70 ˚C for SAB 83C166-5M, SAB 80C166 -40 to +85 ˚C for SAB 83C166-5M-T3, SAB 80C166-M-T3 A Parameter Input low voltage Input high voltage (all except RSTIN and XTAL1) Input high voltage RSTIN Input high voltage XTAL1 ...
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... A voltage sufficient to retain the content of the internal RAM during power down mode. CC Figure 8 Supply/Idle Current as a Function of Operating Frequency Semiconductor Group and 20 MHz CPU clock with all outputs open. CCmax 31 SAB 80C166/83C166 – 0 all outputs CC CC REF ...
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... A/D Converter Characteristics +70 ˚C for SAB 83C166-5M, SAB 80C166 -40 to +85 ˚C for SAB 83C166-5M-T3, SAB 80C166-M- 4.0 V +0.1 V; AREF CC Parameter Analog input voltage range Sample time Conversion time Total unadjusted error Internal resistance of reference ...
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... For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded mA Figure 10 Float Waveforms Semiconductor Group V min for a logic ‘1’ and SAB 80C166/83C166 max for a logic ‘0’ level occurs OH OL ...
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... AC Characteristics External Clock Drive XTAL1 +70 ˚C for SAB 83C166-5M, SAB 80C166 -40 to +85 ˚C for SAB 83C166-5M-T3, SAB 80C166-M-T3 A Parameter Symbol Oscillator period TCL High time Low time t t Rise time t Fall time Figure 11 ...
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... AC Characteristics (cont’d) Multiplexed Bus +70 ˚C for SAB 83C166-5M, SAB 80C166 -40 to +85 ˚C for SAB 83C166-5M-T3, SAB 80C166-M- (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 ALE cycle time = 6 TCL + 2 Parameter ...
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... Semiconductor Group Symbol Max. CPU Clock = 20 MHz min. max – – – SAB 80C166/83C166 Variable CPU Clock 1/2TCL = MHz min. max. 2TCL - 15 – 2TCL - 15 – 2TCL - 15 – Unit ...
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... BUS RD Write Cycle BUS WR Figure 12-1 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE Semiconductor Group Address t 7 Address Address Data Out SAB 80C166/83C166 Data ...
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... BUS RD Write Cycle BUS WR Figure 12-2 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor Group Address t 7 Address Address SAB 80C166/83C166 Data Data Out t 22 ...
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... Read Cycle BUS RD Write Cycle BUS WR Figure 12-3 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group Address t 7 Address Address Data Out SAB 80C166/83C166 Data ...
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... Read Cycle BUS RD Write Cycle BUS WR Figure 12-4 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor Group Address t 7 Address Address SAB 80C166/83C166 Data Data Out t 22 ...
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... AC Characteristics (cont’d) Demultiplexed Bus +70 ˚C for SAB 83C166-5M, SAB 80C166 -40 to +85 ˚C for SAB 83C166-5M-T3, SAB 80C166-M- (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 ALE cycle time = 4 TCL + 2 Parameter ...
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... ALE rising edge after RD, WR Address hold after RD, WR Semiconductor Group Symbol Max. CPU Clock = 20 MHz min. max - – – SAB 80C166/83C166 Variable CPU Clock 1/2TCL = MHz min. max. -10 – – Unit ns ns ...
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... Read Cycle BUS (D15-D8) D7-D0 RD Write Cycle BUS (D15-D8) D7-D0 WR Figure 13-1 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Semiconductor Group Address SAB 80C166/83C166 Data Data Out ...
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... Read Cycle BUS (D15-D8) D7-D0 RD Write Cycle BUS (D15-D8) D7-D0 WR Figure 13-2 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor Group Address Data Out SAB 80C166/83C166 Data ...
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... BHE t Read Cycle BUS (D15-D8) D7-D0 RD Write Cycle BUS (D15-D8) D7-D0 WR Figure 13-3 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group Address SAB 80C166/83C166 Data Data Out ...
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... BHE t 6 Read Cycle BUS (D15-D8) D7-D0 RD Write Cycle BUS (D15-D8) D7-D0 WR Figure 13-4 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor Group Address Data Out SAB 80C166/83C166 Data ...
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... AC Characteristics (cont’d) CLKOUT and READY +70 ˚C for SAB 83C166-5M, SAB 80C166 -40 to +85 ˚C for SAB 83C166-5M-T3, SAB 80C166-M- (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF L Parameter CLKOUT cycle time ...
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... The next external bus cycle may start here. Semiconductor Group order to be safely synchronized. This is guaranteed SAB 80C166/83C166 READY 6) MUX/Tristate waitstate see ...
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... AC Characteristics (cont’d) External Bus Arbitration +70 ˚C for SAB 83C166-5M, SAB 80C166 -40 to +85 ˚C for SAB 83C166-5M-T3, SAB 80C166-M- (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF L Parameter HOLD input setup time ...
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... BREQ Other Signals Figure 15 External Bus Arbitration, Releasing the Bus Notes 1) The SAB 80C166 will complete the currently running bus cycle before granting bus access. 2) This is the first possibility for BREQ to get active. Semiconductor Group SAB 80C166/83C166 2) ...
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... Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the SAB 80C166 requesting the bus. 2) The next SAB 80C166 driven bus cycle may start here Semiconductor Group SAB 80C166/83C166 2) ...