PDSP16510AA0AC Mitel Networks Corporation, PDSP16510AA0AC Datasheet
PDSP16510AA0AC
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PDSP16510AA0AC Summary of contents
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Supersedes version in December 1993 Digital Video & DSP IC Handbook, HB3923-1 The PDSP16510 performs Forward or Inverse Fast Fourier Transforms on complex or real data sets containing up to 1024 points. Data and coefficients are each represented by 16 ...
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PDSP16510 N D9 D10 D12 M D8 D11 GND LFLG F VDD R10 A R9 ...
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SIGNAL TYPE DESCRIPTION D15:0 I Data input during real only mode. The real component in complex data mode. AUX15:0 I When DEF is active AUX15:0 are used to define the operating mode as defined in Table 3. When DEF is ...
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PDSP16510 spaced frequencies are to be detected, and one is of smaller magnitude than the other. It does, however, reduce the actual frequency resolution, and the Hamming window may then be preferable. Data in and out of the device is ...
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Overflow can NEVER occur if the 3 bit option is chosen, but at the expense of worse dynamic range. When overflow does occur a flag is raised which can be read ...
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PDSP16510 noted that the amount of overlap between I/O transfers and transforms is completely under the control of the system, since an input enable signal (INEN) and an output enable (DEN) can be used to initiate transfers. In the 1024 ...
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SCLK). If this causes a system limitation in a single device application, then the device can be configured for pseudo, Mode 2, multiple device operation. Separate load, transform, and then dump operations will then always occur, but DEN ...
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PDSP16510 with a number of DOS strobes (see "user notes - stopping DOS") once a transform is complete in order to transfer data to the output pins. DAV will not go active until this priming has occurred. The state of ...
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When DEN and DOS are both active an internal read operation occurs, and an address generator is incremented. DAV goes in-active in response to the DOS edge needed to read the last output, unless Bit 15 in the Control ...
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PDSP16510 AUX O/P PDSP16510 DIN S3:0 SYSTEM CLOCK Fig. 7. Host Controlled System data and scale tag outputs will go high impedance after the delay shown in Table 3. Valid transformed data is actually available within the device from DAV ...
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In a single device system, performing non overlapped transforms on data from a SINGLE source, only the Real input pins are used, and the Imaginary inputs are redundant except when configuring the device. By setting Control Register Bits 8:6 to ...
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PDSP16510 given previously. The time taken to dump the transformed data must be no more than the load time, if continuous inputs are to be supported and I/O operations are concurrent with transforms. With block overlapping the dump time must ...
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Data). This bit must not be set in the other devices. Since all devices are supplied from a common input bus and have a common source of control parameters, this Bit 12 inversion is best mechanized with an Exclusive OR ...
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PDSP16510 occur, until DEN is finally received. This modification to the internal control logic ensures that the output buffer does not impose unnecessary gaps between consecutive transforms. These gaps would, in turn, force the required DOS frequency to be greater ...
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SCLK. In this mode increasing the output clock frequency will allow a greater continuous input rate. separate DIS and DOS pins allows this to be mechanized, and the DOS frequency can be increased to that of ...
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PDSP16510 firstly through the Auxiliary inputs and then through the Real inputs. BIT 10:9 These bits define a single device system, or one of three multiple device possibilities. The choice between the first and second multiple device mode is dependent ...
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REAL IMAG' PARAMETERS POWER DATA DATA ON RESET XR XI AUX PDSP16116 COMPLEX PDSP16510 MULTIPLIER CLK ZERO WINDOW COUNTER PROM CLR Fig. 11. External Window Generator window it is six bins. The latter two windows are actually ...
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PDSP16510 Arithmetic Accuracy Max Tone WRT Noise 16 bit,unconditional 60 scaling 24 bit arithmetic with unconditional scaling bit inputs 16 bit inputs with 74 PDSP16510 block FP Full 32 bit Floating point with 16 bit inputs 93 Table ...
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USER NOTES - STOPPING DOS (1) GENERAL DESCRIPTION The transform is calculated internally fully synchronous to SCLK. However, as all outputs are referenced to DOS, a transfer has to be made between the two clocks. In addition, some dummy DOS ...
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PDSP16510 (4) OUTPUT SCENARIOS Considering the above sequence, therefore, some single device situations can now be explained : (4.1) DOS is continuously present, but DEN is inactive (Transform size less than 1024) In this case, when the transform is complete, ...
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ABSOLUTE MAXIMUM RATINGS [See Notes] Supply voltage Vcc Input voltage V IN Output voltage V OUT Clamp diode current per pin I (see note 2) K Static discharge voltage (HMB) Storage temperature T S Junction Temperature, Commercial Junction temperature, Industrial ...
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PDSP16510 ORDERING INFORMATION PDSP16510A C0 AC PDSP16510A C0 GC PDSP16510A B0 AC PDSP16510A B0 GC PDSP16510A A0 AC PDSP16510A A0 GC PDSP16510A/MA/GCPR 22 ( Commercial -PGA Package ) ( Commercial -Leaded Chip Carrier ) ( Industrial - PGA Package ) ...
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North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. However, Mitel assumes no liability for errors ...