PDSP16488AMA Mitel Networks Corporation, PDSP16488AMA Datasheet

PDSP16488AMA

Manufacturer Part Number

PDSP16488AMA

Description

Single Chip 2D Convolver with Integral Line Delays

Manufacturer

Mitel Networks Corporation

Datasheet

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Supersedes January 1997 version, DS3742 - 3.1

cific, image processing device. It performs a two dimensional

convolution between the pixels within a video window and a

set of stored coefficients. An internal multiplier accumulator

array can be multi-cycled at double or quadruple the pixel

clock rate. This then gives the window size options listed in

Table 1.

either four or eight line delays. The length of each delay can

be programmed to the users requirement, up to a maximum of

1024 pixels per line. The line delays are arranged in two

groups,which may be internally connected in series or may be

configured to accept separate pixel inputs. This allows inter-

laced video or frame to frame operations to be supported.

be downloaded from a host computer or from an EPROM. No

additional logic is required to support the EPROM and a single

device can support up to 16 convolvers.

delay network which allows several devices to be cascaded.

Convolvers with larger windows can then be fabricated as

shown in Table 2.

danger of overflow, but the final result will not normally occupy

all bits. The PDSP16488A thus provides a multiplier in the

output path, which allows the user to align the result to the

most significant end of the 32 bit word.

* Maximum rate is limite d to 30 MHz by line stor e expansion delays

Max Pixel

Data

Size

10MHz

20MHz

40MHz

Table 2 Devices needed to implement typical window sizes

Rate

The PDSP16488A is a fully integrated, application spe-

An internal 32k bit RAM can be configured to provide

The 8 bit coefficients are also stored internally and can

The PDSP16488A contains an expansion adder and

Intermediate 32 bit precision is provided to avoid any

Width X Depth

Pixel

Window Size

Size

Table 1 Single Device Configurations

3x3

5x5

7x7

Window size

Max Pixel

40MHz

20MHz

10MHz

20MHz

10MHz

9x9 11x11 15x15 23x23

Rate

Single Chip 2D Convolver with Integral Line Delays

Line

Delays

4x1024

8x512

4x512

FEATURES

NOTE

Polyimide is used as an inter-layer dielectric and as

glassivation.

Polymeric material is also used for die attach which according

to the requirement in paragraph 1.2.1.b. (2) precludes

catagorising this device as fully compliant. In every other

respect this device has been manufactured and screened in full

accordance with the requirements of Mil-Std 883 (latest revi-

sion).

CHANGE NOTIFICATION

The change notification requirements of MIL-PRF-38535 will

be implemented on this device type. Known customers will be

notified of any changes since the last buy when ordering further

parts if significant changes have been made.

Rev

Date

COMPOSITE

CONVERTER

The PDSP16488A is a fully compatible replacement

for the PDSP16488

8 or 16 bit pixels with rates up to 40 MHz

Window sizes up to 8 x 8 with a single device

Eight internal line delays

Supports interlace and frame to frame operations

Coefficients supplied from an EPROM or remote host

Expandable in both X and Y for larger windows

Gain control and pixel output manipulation

132 pin QFP

EXTRACT

SYNC

A/D

Fig. 1 Typical , Stand Alone, Real Time System

GENERATOR

CLOCK

PIXEL

OPTIONAL

MAR 1993 JUL 1996

STORE

FIELD

PDSP16488A MA

BYPASS

SYNC

DATA

AUX

DATA

CLK

CONVOLVER

ADDR

EPROM

16488A

DS3742 - 4.0 January 2000

PDSP

DATA

PDSP16488A MA

JAN1997

RES

POWER ON

RESET

DELAYED

OUTPUT

SYNC

DATA

Related parts for PDSP16488AMA

PDSP16488AMA Summary of contents

Page 1

Supersedes January 1997 version, DS3742 - 3.1 The PDSP16488A is a fully integrated, application spe- cific, image processing device. It performs a two dimensional convolution between the pixels within a video window and a set of stored coefficients. An internal ...

Page 2

PDSP16488A R/W PC0 PC1 RE S CS3:0 PROG MASTER SINGLE DELOP Y IP7:0 DELAY BY PASS Y L7:0 DELAY PIN NO FUNCTION AC PACKAGE AC PACKAGE SPARE ...

Page 3

NAME TYPE DESCRIPTION IP7:0 INPUT Pixel data input to the first line delay. [most significant byte in 16 bit mode] L7:0 I/O Pixel data input to the second group of line delays. [least significant byte in 16bit mode]. Alternatively an ...

Page 4

PDSP16488A MA BASIC OPERATION The PDSP16488A convolver performs a weighted sum of all the pixels within two dimensional window. Each pixel value is multiplied by a signed coefficient, or weight, and the products are summed together. ...

Page 5

X 3 WINDOW LINE N C10 LINE LINE N WINDOW LINE N-2 C48 C49 C50 C51 C52 LINE N C10 C11 C12 LINE N C44 ...

Page 6

PDSP16488A MA IP7:0 IP7:0 512 BYPASS BYPASS 512 512 512 8X8 ARRAY L7:0 512 512 512 512 L7:0 IP7:0 IP7:0 1024 BYPASS BYPASS 1024 L7 1024 ARRAY 1024 L7:0 L7:0 IP7:0 512 BYPASS ...

Page 7

The function of the gain control is then to produce an output, which is accurate to 16 bits, and which is aligned to the most significant end of this 32 bit word. The sixteen ...

Page 8

PDSP16488A MA INPUT delays 0 D3 delays WIDTH = S line delays 0 ZERO delays 4 clock delay delays 4+S(N-1) Defined by D3:2 delays ...

Page 9

The internal convolver sums, in each of the devices in the next row, must be delayed by this amount before they are added to results from the previous row. This is more conven- iently achieved by delaying data going into ...

Page 10

PDSP16488A MA IP7:0 1024 1024 1024 1024 L7:0 NOTE Two coefficients occuring in the s ame box have identical values 10 IP7:0 512 512 C8 C9 C10 C11 512 C16 C17 C18 C19 512 C24 C25 ...

Page 11

LOADING REGISTERS FROM A HOST CPU The expansion data inputs [X14: single or master device are connected to the host bus to provide address and data for the internal registers multiple device system the remaining devices ...

Page 12

PDSP16488A multiple device system the load sequence will be repeated for every device, and four additional address bits will be generated on the CS3:0 pins. These address bits provide the EPROM with a page address, with one ...

Page 13

BIT 7 This bit must be set if the pixel clock is greater than 20MHz. It disables the output and input time multiplexing, and instead outputs the least signifi- cant half of the 32 bit intermediate sum for the complete ...

Page 14

PDSP16488A MA REGISTER D Bit Allocation CODE FUNCTION BIT 0 0 X15:0 Not delayed 0 1 X15:0 Delayed 1 0 Internal sum not shifted 1 1 Internal sum multiplied by 256 00 I/P to line stores not delayed 3:2 01 ...

Page 15

Characteristic † DS Hold Time after REPLY active † Host Address/data Set Up Time † Read Set UpTime to prevent Write † Host Signal Hold Time † Expansion in to Data Out in PROG m ode † Delay from strobe ...

Page 16

PDSP16488A MA Characteristic † Delay from Data Strobe to MASTER P C1 † Delay from PC0 Input to Write in-a ctive † PC1 In-Active Delay † Write from MASTER In-Active † Write In-Active to new Address † EPROM Data Set ...

Page 17

Characteristic Pixel Clock Low Time * Pixel Clock High Time * Data in Set Up Time * Data in Hold Time * CLK rising to Output delay * Line Store Output Delay * HRES In-active Set Up Time † † ...

Page 18

PDSP16488A MA APPLICATIONS INFORMATION DEVICE REQUIREMENTS The number of devices required to implement a given convolver window depends on the size of the window, the required pixel rate, and whether the pixel accuracy bits. ...

Page 19

The internal convolver sum, in the device producing the final result, must be delayed by 4 pixels to match the inherent delay in the expansion output from the other device. This is ...

Page 20

PDSP16488A MA EPROM GND PIXEL IP7:0 DATA HRES PDSP PDSP SYNC VCC O/C BYPASS 16488A 16488 R/W DELOP GND LEAST SIG L7:0 BYTE OF 16 BIT PIXEL GND O/C PROG ADDRESS DECODE HOST CPU DS O/C PIXEL IP7:0 DATA HRES ...

Page 21

EPROM GND 8 BIT PIXEL IP7:0 DATA SYNC HRES VCC O/C BYPASS L7:0 WINDOW WINDOW R/W GND IP7:0 HRES GND BYPASS O/C L7:0 WINDOW WINDOW R/W GND HOST CPU R/W O/C IP7:0 SYNC HRES ODD BYPASS FIELD L7:0 WINDOW WINDOW ...

Page 22

PDSP16488A MA GC SIG N OEN 4 BIN 5 PC1 VDD 6 GND 7 OVER 8 9 N/C 10 HRES 11 R N GND 16 N GND 18 ...

Page 23

EPROM GND 16 BIT LSB PIXEL IP7:0 DATA SYNC HRES PDSP PDSP 16488A 16488 VCC O/C BYPASS 8X4 L7:0 WINDOW WINDOW R/W GND O/C MSB IP7:0 HRES PDSP PDSP 16488A 16488 O/C BYPASS 8X4 8X4 O/C L7:0 WINDOW WINDOW R/W ...

Page 24

PDSP16488A MA HOST DS CPU R/W PIXEL SYNC DATA O/C IP7:0 PDSP PDSP HRES 16488A 16488 VCC O/C BYPASS L7:0 [MASTER] DS IP7:0 HRES BYPASS GND 16488A L7 PROG IP7:0 HRES CE BYPASS D15:0 VCC O/C L7:0 DS ...

Page 25

EPROM UPPER ADDR BITS PIXEL SYNC DATA GND IP7:0 HRES PDSP PDSP VCC O/C BYPASS 16488A 16488 [MASTER] DS GND O/C FIELD DELAY IP7:0 HRES PDSP PDSP ODD BYPASS FIELD 16488 16488A DS O/C GND Figure 15. Four Device Interlaced ...

Page 26

PDSP16488A MA HOST DS 16 BIT PIXEL R/W DATA SYNC MSB O/C MSB IP7:0 HRES O/C BYPASS VCC LSB L7:0 DS LSB FIELD DELAY MSB MSB IP7:0 HRES BYPASS LSB ODD L7:0 FIELD DS LSB 26 PROG CPU IP7:0 HRES ...

Page 27

EPROM UPPER ADDR DATA IN SYNC GND IP7:0 PDSP PDSP HRES 16488A 16488 [MASTER] BYPASS VCC O/C HRES L7:0 GND IP7:0 PDSP PDSP HRES 16488 16488A GND BYPASS L7:0 GND IP7:0 PDSP PDSP PDSP HRES 1648 16488A 16488 BYPASS GND ...

Page 28

PDSP16488A MA EPROM DATA IN EPROM UPPER UPPER ADDR ADDRESS GND CS3 IP7:0 O/C CE PDSP PDSP SYNC HRES D15:0 16488 16488A VCC O/C BYPASS RES L7:0 GND MST GND GND 4 CLK DELAYS IP7:0 CE PDSP PDSP HRES D15:0 ...

Page 29

Part No: PDSP16488 Single Chip 2D Convolver with Integral Line Delays Package Type: GC132 Pin No. Pin No. Volts N N/C 5 GND GND 8 N ...

Page 30

North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. However, Mitel assumes no liability for errors ...

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