PDSP16488A Zarlink Semiconductor, PDSP16488A Datasheet

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... Note: PDSP16488A devices are not guaranteed to cascade with 43512 PDSP16488 devices. Zarlink Semiconductor do not recommend that PDSP16488A be mixed with PDSP16488 devices in a single 43512 equipment design. The PDSP16488A requires external pullup resistors in EPROM Mode (see Static Electrical Characteristics). ORDERING INFORMATION ...

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... PDSP16488A Signal Type IP7:0 Input Pixel data input to the first line delay (most significant byte in 16-bit mode). L7:0 I/O Pixel data input to the second group of line delays. (least significant byte in 16-bit mode). Alterna- tively an output from the last line delay when the appropriate mode bit is set. ...

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... SINGLE CONTROL DELOP HRES Y IP7:0 DELAY 1 LINE BYPASS DELAY 3 LINE DELAYS Y L7:0 DELAY 4 LINE DELAYS PC1 RES CS3:0 X DELAY COEFFICIENT STORE (64) 838 ARRAY OF MACs CLK Fig. 2 Functional block diagram PDSP16488A BIDIRECTIONAL MULTIPURPOSE DATA BUS X15:0 CONTROL REGISTERS COMPARATOR OEN BIN OVR F1:0 D15:0 3 ...

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... PDSP16488A Fig. 3a Pin connections for 84 I/O pin grid array package - AC84 (Power ) (bottom view) Fig 3b Pin connections for 132 I/O ceramic power flatpack - GC132 (Power) (top view) Fig 3 Pin connection diagrams (not to scale). See Table 3 for signal descriptions and Tables 4 and 5 for pinouts. ...

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... L5 GND N X13 X14 X15 GND DD BYPASS 96 L1 IP0 N/C 99 N/C PDSP16488A Signal Pin Signal B6 D10 A5 D11 B5 N/C PC1 A4 D12 OEN B4 D13 A3 D14 B3 D15 F13 GND1 ...

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... With 16-bit pixels, and an 834 window (the maximum possible), the sum can grow to 29 bits. The PDSP16488A actually allows for word growth bits, and thus allows several devices to be cascaded without any danger of overflow. Since coefficients can be negative, the final result is a 32-bit signed two’ ...

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... This can be achieved by inhibiting write operations until DELOP goes low. Write operations then continue until it goes back high. The PDSP16488A assumes that data is valid when a clock signal is applied, and that it also meets the set up and hold requirements given in Fig. 10. If data is not valid due, for example frame store DRAM refresh cycle, then the user must externally inhibit the clock ...

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... PDSP16488A 333 WINDOW LINE N21 C4 C5 LINE LINE N11 C0 C1 535 WINDOW LINE N22 C48 C49 C50 C51 LINE N21 C8 C9 C10 C11 LINE N C40 C41 C42 C43 LINE N11 LINE N12 C32 C33 C34 C35 838 WINDOW ...

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... Multiple devices can be connected in cascade in order to obtain window sizes larger than those provided by a single PDSP16488A. This requires an additional adder in each device which is fed from expansion data inputs. This adder is not used by a Single device or the first device in a cascaded system, and is enabled or disabled by register B, bit 4 ...

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... Since partial windows can only pixels wide, a delay pixel clocks is needed. There is, however, an in-built delay of 4 pixels in the inter device connection, and the PDSP16488A thus only needs an option to delay the expansion input by an additional four pixels. ...

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... These delays are discussed in the applications section. The PDSP16488A contains facilities for outputting a delayed version of HRES (DELOP) to match any processing delay. Register C. bits 3:1 allow this delay to be selected from any value between 29 and 92 pixel clocks as detailed in Table 9 ...

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... PDSP16488A IP7:0 512 512 512 512 512 512 512 512 L7:0 IP7:0 L7:0 512 512 MSB LSB 512 512 512 512 512 512 IP7:0 1024 1024 1024 1024 L7:0 IP7:0 L7:0 512 512 16 MSB LSB C0 C16 512 512 16 C4 C20 512 512 16 C8 C24 512 ...

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... R/W line The Master device contains internal address counters which allow the registers cascaded PDSP16488As to be specified. It also generates the on the pins which were previously inputs. These outputs must be connected to the other devices in the system, which still use them as inputs ...

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... PDSP16488A EPROM control lines X7:0 8 bit data from the EPROM to the Master or Single device. Otherwise data is received from the previous device in the chain. X14:8 Lower 7 address bits to the EPROM from a Master or Single device. Otherwise an input from the data output of the previous device. ...

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... BITS 3:2 These bits define the delays on both sets of pixel BIT 4 BIT 7:5 Bit 3:2 Function 3:2 3:2 3 7:5 PDSP16488A Code Function 011 DELOP = 29124 clocks 100 DELOP = 29132 clocks 101 DELOP = 29140 clocks 110 DELOP = 29148 clocks 111 DELOP = 29156 clocks 00 Select upper 20 bits 01 ...

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... C to1150 C full accordance with MIL-STD-883 (latest revision). The PDSP16488A MA ACBR (PGA packge) is subject to the 195 C constant acceleration test, Method 2001, Test Condition A (5kg). 1110 C Life test/burn-in connections are given in Tables 12 and 13 on 1150 C the following page ...

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... GND 5· N 5· 5· 5· N/C L1 N10 GND Table 12 Life test/burn-in connections for PDSP16488A MA ACBR (PGA). NOTE: PDA is 5% and based on groups 1 and 7 Pin Voltage 1 N/C 2 N/C 3 15·0V 4 N/C 5 N/C 6 15·0V 7 GND 8 N/C 9 N/C 10 15· ...

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... PDSP16488A Switching Characteristics for Host mode Characteristic hold time after low Host address/data setup time Read setup time to prevent Write Host signal hold time Expansion in to data out in mode PROG Delay from low to PC1 low (Note 2) DS setup time ...

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... RW t PCD t EXP VALID CE DATA OUTPUT FROM FIRST DEVICE DATA OUTPUT FROM SECOND DEVICE Fig. 11 EPROM timing PDSP16488A Conditions Single device Greater than at all temperatures PCH t AD VALID VALID t CSU t t ...

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... PDSP16488A Switching Characteristics, operational timings Characteristic CLK low time CLK high time Data in setup time Data in hold time CLK rising to output delay L7:0 output delay HRES low setup time Output enable time Output disable time X15:0 Expansion setup time X15:0 Expansion hold time ...

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... In practice the PDSP16488A supports windows requiring one, two, four, six, or eight devices without additional logic. Table 2 gives typical window sizes which may be obtained with the above number of devices ...

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... PDSP16488A The least significant 8 bits of the pixel are connected to the Master device and the most significant 8 bits are connected to the device producing the final result.. The internal sum in this device must be delayed by four pixels to match the delay in the expansion output from the first device. This is actually achieved by delaying the pixel inputs to the line stores (register D, bits 4:2, = 001) ...

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... IP7:0 BIN BIN D15:0 DATA OUT DELOP DELAYED SYNC L7:0 OEN OUTPUT ENABLE Interlaced EPROM mode HOST CPU ADDRESS DECODE O/C PROG HRES CE BYPASS RES RESET PDSP16488A IP7:0 BIN BIN D15:0 DATA OUT DELOP DELAYED SYNC L7:0 OEN OUTPUT ENABLE Interlaced 16-bit Host loaded 23 ...

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... HOST CPU R/W REPLY O/C PROG IP7:0 CE PDSP16488A R/W RES 834 HRES WINDOW BYPASS DELOP O/C L7:0 D15:0 FIELD DELAY PROG DS CE PC1 PDSP16488A RES IP7:0 834 D15:0 HRES WINDOW BIN R/W OVR BYPASS V DD OEN L7:0 O/C Interlaced Fig. 14 8-bit dual device systems V DD 15k NOM DELAYED SYNC ...

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... BIN OVR OVERFLOW OEN OUTPUT ENABLE Non-interlaced HOST CPU ADDRESS DECODE O/C PROG CE PDSP16488A RES 834 WINDOW DELAYED DELOP SYNC D15:0 PROG READ REGISTERS CE (TRISTATE ENABLE) PDSP16488A RES D7:0 834 D15:0 DATA OUT WINDOW BIN BIN OVR OVERFLOW OEN OUTPUT ENABLE Interlaced PDSP16488A 25 ...

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... RES HRES V BYPASS DD L7:0 IP7:0 PC1 PC0 PROG DS PDSP16488A CE3 CE R/W (3) RES HRES GND BYPASS L7:0 Fig. 16 Four device non-interlaced system. PC1 PROG PDSP16488A CE CE2 (2) RES DELOP DELAYED SYNC DATA OUT BIN BIN PC1 PROG PDSP16488A CE CE4 (4) RES OVR OVERFLOW OEN OUTPUT ENABLE ...

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... RES HRES V CE O/C BYPASS DD IP7:0 PC1 PC0 PROG DS PDSP16488A CE CE3 (3) R/W GND RES HRES BYPASS Fig. 17 Four device interlaced system. PDSP16488A PC1 PROG CE2 CE (2) RES DELOP DELAYED SYNC DATA OUT BIN BIN PC1 PROG CE CE4 (4) RES OVR OVERFLOW OEN OUTPUT ENABLE ...

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... BYPASS L7:0 IP7:0 PC1 PC0 PROG DS PDSP16488A CE CE3 (3) R/W RES HRES BYPASS L7:0 Fig. 18 Four device system with 16-bit pixels PC1 PROG PDSP16488A CE CE2 (2) RES DELOP DELAYED SYNC DATA OUT BIN BIN PC1 PROG PDSP16488A CE CE4 (4) RES OVR OVERFLOW OEN OUTPUT ENABLE ...

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... HRES V DD BYPASS L7:0 IP7:0 PC1 PC0 PROG DS PDSP16488A CE3 CE GND R/W (4) RES HRES GND BYPASS L7:0 IP7:0 PC1 PC0 PROG DS PDSP16488A CE5 CE R/W (6) GND RES HRES GND BYPASS O/C L7:0 PDSP16488A PC1 PROG CE CE2 RES DELOP DELAYED SYNC PC1 PROG CE CE4 RES DATA OUT BIN ...

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... V BYPASS DD IP7:0 PC1 PC0 DS PROG PDSP16488A CE4 GND CE CE5 R/W (5) HRES RES GND BYPASS IP7:0 PC0 PC1 DS PROG PDSP16488A CE7 GND R/W (8) CE CE8 HRES RES GND BYPASS DELAYED SYNC Fig. 20 Nine device non-interlaced system 15k 15k NOM NOM PROG DS IP7:0 ...

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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...