PDSP16318 Mitel Networks Corporation, PDSP16318 Datasheet
PDSP16318
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PDSP16318 Summary of contents
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... Adder/Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 20MHz throughout in FFT and filter applications. Two PDSP16318As combined with a single PDSP16112A Complex Multiplier provide a complete arithmetic solution for a Radix 2 DIT FFT Butterfly. A new complex Butterfly result can be generated every 50ns allowing 1K complex FFTs to be executed in 256 s ...
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... PDSP16318/16318A CEA CYCLE A REG A DELAY CLK 16 16 REG B CEB 2 DEL ASR S2:0 20 MUX B 20 SHIFT A 20 REG MUX MUX REG 20 A SHIFT 20 B ASI Fig. 3 Block diagram OEC 16 16 REG D CLR OVR 16 16 REG D OED ...
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... FFT applications to ensure correct phasing of data that has not passed through the PDSP16112 Complex Multiplier. The 16-bit outputs from the PDSP16318 are derived from the 20-bit result generated by the Adders. The three bit S2:0 input selects eight different shifted output formats ranging from the most significant 16 bits of the 20-bit data, to the least significant 13 bits of the 20-bit data ...
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... PDSP16318/16318A GC pin Function D10 85 GND 86 VCC 87 D11 88 D12 89 D13 90 D14 91 D15 92 C15 93 C14 94 C13 95 C12 96 VCC 97 GND 98 C11 99 C10 100 ASR or ASI ALU Function ASX1 ASX0 S2 ...
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... C to +125 C 150 C Delay from output high impedance to 1000mW Output low Delay from output high impedance to Output high NOTES Voltage reached when output driven high Voltage reached when output driven low C PDSP16318/16318A Test Waveform - measurement level V H 0.5V 0. 1.5V 0.5V 0.5V 1. 1.5V I ...
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... OL Units Conditions - 3.2mA =-3.2mA GND < V < GND <V OUT Max Value Military Units PDSP16318 Min. Max. Max. ns 100 - - ...
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