PDSP16116MC Zarlink Semiconductor, PDSP16116MC Datasheet - Page 6

• Manufacturer Part Number: PDSP16116MC
• Description: 16 by 16 Bit Complex Multiplier
• Manufacturer: Zarlink Semiconductor

PDSP16116/A/MC
NORMAL MODE OPERATION
mode of operation is selected.
Complex Multiply operations that do not require Block Floating
Point arithmetic.
Multiplier Satge
the X and Y input registers via the X and Y Ports on the rising
edge of CLK. The Real and Imaginary components of the
fractional data are each assumed to have the following format
Where S = sign bit which has an effective weighting -2 0
The value of the 16 bit two’s complement word is
Value = (-1xS)+(bit14x2 -1 )+(bit13x2 -2 )+(bit12x2 -3 ). . .
to be permanently enabled, then these signals may be tied to
ground. On each clock cycle the contents of the input registers
are passed to the four multipliers to start a new Complex
Multiply operation. Each Complex Multiply operation requires
four partial products (Xr x Yr), (Xr x Yi), (Xi x Yr), (Xi x Yi), all
of which are calculated in parallel by the four 16 x 16
Multipliers. Only one clock cycle is required to complete the
multiply stage before the Mutliplier results are loaded into the
Multiplier output registers for passing on to the Adder/
Subtractors in the next cycle. Each multiplier produces a 31
bit result with the duplicate sign bit eliminated. The format of
the output data from the Multipliers is
The effective weighting of the sign bit is -2 0
Result Correction
representation it is possible to represent -1 exactly but not 1.
With conventional multipliers this causes a problem when -1
is multiplied by -1 as the multiplier produces an incorrect
result. The PDSP16116 includes a trap to ensure that the
most positive number (value = 1.2 -30 ), (hex = 7FFFFFFFF) is
subsituted for the incorrect result. The multiplier result is
therefore always a (correct) fractional value.
Complex Conjugation
asserting the CONX or CONY signals respectively. Asserting
either of these signals has the effect of inverting (multiplying
by -1) the imaginary component of the respective input. Table
3 shows the effect of CONX and CONY on the X and Y inputs.
6
BIT NUMBER
WEIGHTING
BIT NUMBER
WEIGHTING
When the MBFP mode select input is held low the ‘Normal’
Complex two's complement fractional data is loaded into
The X & Y port registers are individually enabled by the
Due to the nature of the fraction twos complement
Either the X or Y input data may be complex conjugated by
&
15
30
S
S
signals respectvely. If the registers are required
2
2
14
29
-1
-1
13
2
28
2
-2
-2
12
2
27
2
-3
-3
11
2
26
2
-4
-4
10
2
25
2
-5
-5
2
24
2
9
-6
-6
. . .
. . .
2
8
-7
2
This mode supports all
2
7
7
-23
-8
2
2
6
6
-24
-9
2
2
5
-10
5
-25
2
2
4
-11
4
-26
2
2
3
-12
3
-27
2
2
2
-13
2
-28
2
2
1
-14
1
-29
2
2
0
-15
0
-30
Adder / Subtractor Stage
are passed to two 32 bit Adder/Subtractors. The Adder
calculates the imaginary result ((Xr x Yi) + (Xi x Yr)) and the
Subtractor calculates the Real result ((Xr x Yr) = (Xi x Yi)).
Each Adder/Subtractor produces a 32 bit result with the
following format.
The effective weighting of the sign bit is -2 1
Rounding
significant 16 bits of the full 32 bit result from the Adder/
Subtractor. If the ROUND signal is active (High), then bit 16
is set to a one, rounding the most significant 16 bits of the
Adder/Subractor result. (The least siginificant 16 bits are
unaffected). Inserting a one ensures that the rounding error
is never greater than 1LSB, and that no DC bias is introduced
as a result of the rounding processes.
The format of the Rounded result is;
The effective weighting of the sign is -2 1
Shifter
controlled via the WTB control input. These shifters can each
apply four different shifts, however the same shift is applied to
both real and imaginary components. The four shift options
are:
i) WTB1:0 = 11 Shift complex product one place to the left
giving a shifter output format:
The effective weighting of the sign bit is -2 0
BIT NUMBER
WEIGHTING
BIT NUMBER
WEIGHTING
BIT NUMBER
WEIGHTING
FUNCTION
X x Y
X x Conj Y
Conj X x Y
Invalid
The 31 bit Real and Imaginary results from the Multipliers
The ROUND control when asserted rounds the most
Each of the two Adder/Subtractors are followed by Shifters
31
31
31
S
S
S
30
30
2
2
30
2
-1
0
0
ROUNDED VALUE
29
2
29
2
29
2
-1
-1
-2
Table 3 Conjugate Functions
2
2
2
28
28
28
OPERATION
(XR+XI)x(YR+YI)
(XR+XI)x(YR-YI)
(XR-XI)x(YR+YI)
Invalid
-2
-2
-3
27
2
27
2
27
2
-3
-3
-4
2
. . .
. . .
2
26
26
-4
-5
2
. . .
. . .
18
25
2
-12
-6
2
2
. . .
. . .
17
8
-22
-13
2
2
2
16
7
7
-23
-14
-24
2
2
2
15
6
-24
6
-25
-15
CONX
low
high
low
high
2
2
2
14
5
5
-25
-26
16
2
2
2
13
4
-26
-17
4
-27
LBS's
2
2
. . .
. . .
3
-27
3
-28
2
2
2
2
-28
2
2
-29
-28
CONY
low
low
high
high
2
2
2
1
1
-29
1
-29
-30
2
2
2
0
-30
0
-30
0
-31