PDSP1601-MC Mitel Networks Corporation, PDSP1601-MC Datasheet
PDSP1601-MC
Related parts for PDSP1601-MC
PDSP1601-MC Summary of contents
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... The PDSP1601 can also be cascaded to produce wider words at the 10MHz rate using the Carry Out and Carry In pins. The Barrel Shifter is capable of extension, for example the PDSP1601 can used to select a 16-bit field from a 32-bit input in 100ns. GC pin Function ...
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... PDSP1601 MC PIN DESCRIPTIONS Pin No. Symbol (GG100 Package) ALU B-input multiplexer select control. MSB 16 of CLK. Shifter Input multiplexer select control. MSS 17 of CLK. B Port data Input. Data presented to this port is latched into the input register on the rising B15 - edge of CLK. B15 is the MSB. ...
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... BFP A CO LEFT REG. FUNCTIONAL DESCRIPTION The PDSP1601 contains four main blocks: the ALU, the Barrel Shifter and the two Register Files. The ALU The ALU supports 32 instructions as detailed in Table 1. The inputs to the ALU are selected by the A and B MUXs. Data will fall through from the selected register through the input MUXs and the ALU to the ALU output register file in 100ns ...
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... PDSP1601 MC Table 1 ALU instructions Inst IA4-IA0 00 00000 01 00001 02 00010 03 00011 04 00100 05 00101 06 00110 07 00111 08 01000 09 01001 0A 01010 0B 01011 0C 01100 0D 01101 0E 01110 0F 01111 Inst Inst IA4-AI0 18 11000 19 11001 1A 11010 1B 11011 1C 11100 1D 11101 1E 11110 1F 11111 KEY input to ALU input to ALU CI = External Carry in to ALU ...
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... The shift control block contains a priority Operation I Direction YY = Source of Shift Value X = Direction YY = Source of Shift Value = Direction YY = Source of Shift Value XX = Target YY = Source PDSP1601 MC 5 ...
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... PDSP1601 MC SV3 SV2 SV1 SV0 Table 3 Barrel shifter codes ...
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... NOPPS No load Operation, Pass Barrel Shifter Result Table 4 ALU and shift register instructions mnemonics Load XX = Target Source of Output XX = Source of Output The register file instructions (see Table 4) allow input data The register file instructions allow the output to be sourced Operation Operation PDSP1601 MC 7 ...
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... PDSP1601 MC Multiplexers There are four user selectable on-chip multiplexers (A- MUX, B-MUX, S-MUX and C-MUX). These four multiplexers support instructions as tabulated in Table 5. MARAX A-MUX MAAPR MABPR MARSX B-MUX S-MUX C-MUX 8 The MUX instructions are latched such that the instruction will not start executing until the rising edge of CLK latches the instruction onto the device ...
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... The inverse A input to the ALU is logically 'ORed' with the B input. ORNAB <15> The A input to the ALU is logically Exclusive-ORed with the B input. XORAB <16> The A input to the ALU is passed to the output. PASXA <17> The inverse of the A input to the ALU is passed to the output. PASNA Function Function PDSP1601 MC 9 ...
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... PDSP1601 MC ALU Control Instructions Op Code Mnemonic <18> The BFP flag is programmed to activate when an ALU operation causes an overflow of the SBFOV 16 bit number range. This flag is logically the exclusive-or of the carry into and out of the MSB of the ALU. For the most significant Byte this flag indicates that the result of an arithmetic two's complement operation has overflowed into the sign bit ...
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... MSB and the next most significant bit being different. This has the effect of eliminating unnecessary Sign Bits, and hence Normalising the input data. The MSBs shifted out to the left are discarded, and the vacant LSBs on the right are filled with zeros. Function PDSP1601 MC 11 ...
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... PDSP1601 MC Barrel Shifterl or ALU Register Instructions Op Code Mnemonic <0> After the rising edge of CLK at the beginning of the cycle in which this instruction is LLRRR executed, the contents of the Right register will appear on the output. On the rising edge of CLK at the end of the cycle, the data on the register inputs will be loaded into the Left Register. < ...
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... MS Byte Bit 16 bits The 32 bit words are fed into the B port of the PDSP1601 in two cycles, MS byte first. The PDSP1601 shift control is initiated by programming the R1 and R2 registers with n and 16-n respectively. The shift operation is implemented in three steps:- (1) The MS byte is logically left shifted (16-n) places, the MSBs being discarded and the LSB spaces being filled with zeros ...
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... PDSP1601 MC ELECTRICAL CHARACTERISTICS Operating Conditions (unless otherwise stated) T (Military +125 C, V AMB Static Characteristics Characteristic * Output high voltage * Output low voltage * Input high voltage * Input low voltage * Input leakage current * Vcc current * Output leakage current † Output S/C current † Input capacitance ...
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... Part No: PDSP1601 MC ALU and Barrel Shifter Package Type: GC100 Pin No. Pin No. Volt ...
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