PDSP1601 Mitel Networks Corporation, PDSP1601 Datasheet
PDSP1601
Related parts for PDSP1601
PDSP1601 Summary of contents
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... The PDSP1601 can also be cascaded to produce wider words at the 20MHz rate using the Carry Out and Carry In pins. The Barrel Shifter is also capable of extension, for example the PDSP1601 can used to select a 16-bit field from a 32-bit input in 100ns. FEATURES 16-bit, 32 instruction 20MHz ALU ...
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... PDSP1601/PDSP1601A PIN DESCRIPTION AC pin SIG 1 N/C 2 N/C 3 N/C 4 N/C 5 VCC RA0 8 RA1 9 RA2 IA0 12 IA1 13 IA2 14 IA3 15 IA4 16 MSB 17 MSS 18 B15 19 B14 20 B13 21 B12 22 B11 23 B10 N/C = not connected - leave open circuit ...
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... These inputs are latched internally on the rising 1 This input is latched internally on the rising edge 1 These inputs are latched internally on the 1 These inputs are latched internally on the 1 These inputs are latched internally on the rising 1 IA4 = MSB. These inputs are latched internally on the rising PDSP1601/PDSP1601A 3 ...
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... BFP A CO LEFT REG. FUNCTIONAL DESCRIPTION The PDSP1601 contains four main blocks: the ALU, the Barrel Shifter and the two Register Files. The ALU The ALU supports 32 instructions as detailed in Table 1. The inputs to the ALU are selected by the A and B MUXs. Data will fall through from the selected register through the input MUXs and the ALU to the ALU output register file in 50ns for the PDSP1601A (100ns for the PDSP1601) ...
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... Output 00FF Hex OPNIB Output 000F Hex OPALT Output 5555 Hex MNEMONICS CLRXX MIAXX A2XXX APBXX AMBXX BMAXX ANX-Y ORX-Y XORXY PASXX SBFXX OPXXX PDSP1601/PDSP1601A Function Mode --------- LSBYTE CASCADE MULTICYCLE MSBYTE MULTICYCLE MULTICYCLE MULTICYCLE CASCADE MULTICYCLE LSBYTE CASCADE MULTICYCLE LSBYTE CASCADE ...
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... MUX. Data will fall through from the selected register, through the S MUX and the Barrel Shifter to the shifter output register file in 50ns for the PDSP1601A (100ns for the PDSP1601). The Barrel Shifter instructions are latched, such that the instructions will not start executing until the rising edge of CLK latches the instruction into the device ...
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... Table 3 Barrel shifter codes Priority Encoder If the priority encoder is selected as the source of the shift value (instructions:- NRMXX, NRMR1, MRMRZ), then within one 100ns cycle or two 50ns cycles for the PDSP1601A (one 200ns or two 100ns cycles for the PDSP1601), the shift circuitry will: 16 ...
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... PDSP1601/PDSP1601A The Register Files There are two on-chip register files (ALU and Shifter), each containing two 16 bit registers and each supporting 8 instructions (see Table 4). The instructions for the ALU register file and the Barrel Shifter Register file are the same. The Inputs to the register files come from either the ALU or the Barrel Shifter, and are loaded into the Register files on the rising edge of CLK ...
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... A-PORT INPUT 0 1 B-PORT INPUT 1 0 SHIFTER REGISTER FILE OUTPUT 1 1 MSB B-PORT INPUT 0 SHIFTER REGISTER FILE OUTPUT 1 MSS B-PORT INPUT 0 SHIFTER REGISTER FILE OUTPUT 1 MSC ALU REGISTER FILE OUTPUT 0 SHIFTER REGISTER FILE OUTPUT 1 Table 5 PDSP1601/PDSP1601A Output Output Output Output 9 ...
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... PDSP1601/PDSP1601A INSTRUCTION SET ALU Arithmetic Instructions Op Code Mnemonic <00> On the rising edge of CLK at the end of the cycle in which this instruction is executing, the CLRXX A Port, B Port, ALU, Barrel Shifter, and Shift Control Registers will be loaded with zeros. The internal registered CO will also be set to zero, and the BFP flag will be set to activate on overflow conditions. < ...
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... MSBs are filled with zeros. <7> The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the LSLR2 magnitude of the four bit number resident within the R2 register. The LSBs are discarded, and the vacant LSBs are filled with zeros. PDSP1601/PDSP1601A Function Function 11 ...
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... PDSP1601/PDSP1601A Op Code Mnemonic <8> On the rising edge of CLK at the end of the cycle in which this instruction is executing, the LR1SV R1 register will be loaded with the data present on the SV port. The input to the Barrel Shifter will be passed onto the output unshifted. <9> On the rising edge of CLK at the end of the cycle in which this instruction is executing, the LR2SV R2 register will be loaded with the data present on the SV port ...
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... After the rising edge of CLK at the beginning of the cycle in which this instruction is NOPPS executed, the input to the registers will appear on the output. On the rising edge of CLK at the end of the cycle no load operation will occur, the register contents will remain unchanged. PDSP1601/PDSP1601A Function 13 ...
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... MS Byte Bit 16 bits The 32 bit words are fed into the B port of the PDSP1601 in two cycles, MS byte first. The PDSP1601 shift control is initiated by programming the R1 and R2 registers with n and 16-n respectively. The shift operation is implemented in three steps:- (1) The MS byte is logically left shifted (16-n) places, the MSBs being discarded and the LSB spaces being filled with zeros ...
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... -8mA GND < V < - +85 C amb A GND < V < V OUT Max CC pF PDSP1601A Units Conditions Min. Max LSTTL + 20pF LSTTL + 5pF LSTTL + 5pF ...
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