HT48RA0-5 Holtek Semiconductor, HT48RA0-5 Datasheet - Page 11

• Manufacturer Part Number: HT48RA0-5
• Description: Remote Type 8-Bit OTP MCU
• Manufacturer: Holtek Semiconductor

The chip reset status of the registers is summarised in the following table:
Note:
Input/Output Ports
There are up to 17 bidirectional input/output lines in the
device, labeled PA, PB and PC which are mapped to
[12H], [14H] and [16H] of the Data Memory, respec-
tively. Each line of PA and PB can be selected as NMOS
output or Schmitt trigger input with pull-high resistor by a
software instruction. PC0 can be used as an input line
with Schmitt trigger but without pull-high resistor or as
the external RES pin determined by the configuration
option.
When the I/O ports are used for input operation, these
ports are non-latched, that is, the inputs should be ready
at the T2 rising edge of the instruction MOV A, [m]
(m=12H, 14H or 16H). For I/O ports output operations,
all data is latched and remains unchanged until the out-
put latch is rewritten.
When the I/O Ports are used for input operations, it
should be noted that before reading data from the pads,
Rev.1.00
Program Counter
MP
ACC
TBLP
TBLH
STATUS
PA
PB
PC
TSR0
TSR1
CARL0
CARL1
CARH0
CARH1
Register
u means unchanged
x means unknown
- stands for unimplemented
(Power On)
1111 1111
1111 1111
0000 0000
1000 0000
0000 0000
0000 0000
0000 0000
0000 0010
xxxx xxxx
xxxx xxxx
-xxx xxxx
--00 xxxx
--xx xxxx
---- ---1
Reset
000H
RES or LVR
uuuu uuuu
uuuu uuuu
1111 1111
1111 1111
0000 0000
1000 0000
0000 0000
0000 0000
0000 0000
0000 0010
-uuu uuuu
--uu uuuu
--uu uuuu
---- ---1
Reset
000H
11
a 1 should be written to the related bits to disable the
NMOS device. That is, the instruction SET [m].i (i=0~7
for PA and PB, i=0 for PC) is executed first to disable re-
lated NMOS device, and then MOV A, [m] to get stable
data.
After chip reset, the I/O Ports remain at a high level input
line. Each bit of the I/O ports output latches can be set or
cleared by the SET [m].i and CLR [m].i (m=12H, 14H
or 16H) instructions respectively.
Some instructions first input data and then follow the
output operations. For example, SET [m].i , CLR [m] ,
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or to the accumulator.
Each line of the I/O ports has a wake-up capability when
the relevant pin is configured as an input line.
CPL [m] and CPLA [m] read the entire port states
(Normal Operation)
WDT Time-out
uuuu uuuu
uuuu uuuu
1111 1111
1111 1111
0000 0000
1000 0000
0000 0000
0000 0000
0000 0000
0000 0010
-uuu uuuu
--uu uuuu
--1u uuuu
---- ---1
000H
WDT Time-out
HT48RA0-5
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--uu uuuu
--11 uuuu
March 23, 2010
(HALT)*
---- ---u
000H
www.DataSheet4U.com