HT48R54A Holtek Semiconductor, HT48R54A Datasheet
HT48R54A
Related parts for HT48R54A
HT48R54A Summary of contents
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... All instructions instruction cycles Bit manipulation instructions Up to 0.5 s instruction cycle with 8MHz system clock 44/52-pin QFP package timer, as well as low cost, enhance the versatility of these devices to suit a wide range of application possi- bilities such as industrial control, consumer products, subsystem controllers, etc. 1 HT48R54A July 27, 2007 ...
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... Block Diagram www.DataSheet4U.com Rev. 1.00 HT48R54A 2 July 27, 2007 ...
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... Real time clock oscillator. OSC3 and OSC4 are connected to a 32768Hz crys- tal oscillator for system clock timing purposes. Positive power supply PB port positive power supply PC port positive power supply Negative Power supply, ground PD & PE port negative power supply, ground 3 HT48R54A Description July 27, 2007 ...
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... SYS load, system HALT load, system HALT load, system HALT load, system HALT 5V 2.1V option 3.15V option 4.2V option 3V V =0. =0. HT48R54A Ta=25 C Min. Typ. Max. Unit 2.2 5.5 3.3 5.5 V 2.2 5.5 1.2 2 =4MHz mA 2.5 5 =8MHz 100 ...
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... V =0. Test Conditions Parameter V Conditions DD 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3.3V~5. With prescaler (f /4096) S With prescaler (f /4096) S Power-up or wake-up from HALT 5 HT48R54A Min. Typ. Max. Unit 100 Ta=25 C Min. Typ. Max. Unit 400 4000 kHz 400 ...
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... Program Counter+2 *11 * #11 # S11 S10 Program Counter S11~S0: Stack register bits @7~@0: PCL bits 6 HT48R54A * ...
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... Table Location P11~P8: Current program counter bits 7 HT48R54A TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR, therefore errors may occur ...
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... This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag Rev. 1.00 HT48R54A RAM Mapping (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers ...
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... Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable) Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable) External interrupt request flag (1=active; 0=inactive) Internal Timer/Event Counter 0 request flag (1=active; 0=inactive) Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) Unused bit, read as 0 INTC (0BH) Register 9 HT48R54A Function Function July 27, 2007 ...
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... WDT oscillator will keep running with a period of approximately 5V. The WDT os- cillator can be disabled by a configuration option to con- serve power. System Oscillator 10 HT48R54A should be July 27, 2007 ...
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... Note that if the 32768Hz system clock is selected, then the WDT clock source configura- tion option must also select the 32768Hz oscillator as its clock source, otherwise unpre- dictable system operation may occur. Unused bit, read as 0 32768Hz OSC quick start-up 0=quick start; 1=slow start Unused bit, read as 0 MODE (20H) Register 11 HT48R54A July 27, 2007 ...
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... Most registers are reset to their initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets . TO PDF Note: u stands for unchanged 12 HT48R54A RC Oscillator 32768Hz Off On x Off On ...
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... HT48R54A Reset Circuit RES Reset WDT Time-out (HALT) (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ...
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... As clock blocking may result in a counting error, this must be taken into consideration by the pro- grammer. The bit2~bit0 of the TMR0C can be used to define the pre-scaling stages of the internal clock sources of the timer/event counter 0. The definitions are as shown. Timer/Event Counter 0 14 HT48R54A July 27, 2007 ...
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... But in the other two modes the T1ON can only clock. INT1 be reset by instructions. The overflow of the timer/event counter 1 is one of the wake-up sources. No matter what the operation mode is, writing ET1I can disabled the corresponding interrupt service. 15 HT48R54A Function July 27, 2007 ...
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... To enable or disable timer 1 counting (0=disable; 1=enable) T1S Select clock source of TMR1 (0=f Define the operating mode, T1M1, T1M0= 01=Event count mode (external clock) T1M0 10=Timer mode (internal clock) T1M1 11=Pulse width measurement mode 00=Unused TMR1C (11H) Register 16 HT48R54A Function ; 1=f ) SYS RTC July 27, 2007 ...
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... There is a pull-high option available for PA0~PA7 lines (port option). Once the pull-high option of an I/O line is selected, the I/O line have pull-high resistor. Otherwise, the pull-high resistor is absent. It should be noted that a non-pull-high I/O line operating in input mode will cause a floating state. PA Input/Output Ports 17 HT48R54A July 27, 2007 ...
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... Rev. 1.00 PB Input/Output Ports PC Output Ports PD0 Input/Output Port PD1~PD7, PE Output Ports 18 HT48R54A July 27, 2007 ...
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... I/P (Normal) O/P (Normal) Logical Input Logical Output Timer Preload Value PA7 Data Register HT48R54A PA Data Register Output Function PA1 x PA0=BZ, PA1=BZ x PA0=0, PA1=0 x PA0=BZ, PA1=input x PA0=0, PA1=input D PA0=input, PA1=0 x PA0=input, PA1=input I/P (PFD) O/P (PFD) Logical Input PFD (Timer on) ...
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... LVR will ignore it and do not perform a reset function. The LVR uses the OR function with the external RES signal to perform a chip reset. and V is shown below. DD LVR Low Voltage Reset 20 HT48R54A ) has to remain in their LVR July 27, 2007 ...
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... Timer/event counter 0 clock sources LVR enable or disable 9 LVR voltage: 2.1V or 3.15V or 4.2V 10 Buzzer function: single BZ enable or both BZ and BZ or both disable 11 Buzzer frequency PA7: Normal I/O or PFD output Rev. 1.00 Options /4 or 32768Hz oscillator SYS / SYS SP /2, f /4, f / HT48R54A July 27, 2007 ...
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... For applications where noise may interfere with the reset circuit and for details on the oscillator external components, refer to Application Note HA0075E for more information. Rev. 1.00 falls below its operating range recommended that R1 is added. The values of C1 and HT48R54A July 27, 2007 ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.00 Instruction Description 23 HT48R54A Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 Description (2) 24 HT48R54A Instruction Flag Cycle Affected 2 None (2) 1 None ...
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... The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x TO PDF Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m] TO PDF HT48R54A July 27, 2007 ...
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... The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr TO PDF Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H TO PDF HT48R54A July 27, 2007 ...
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... TO and PDF flags remain unchanged. WDT 00H* PDF and PDF Complement data memory Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] TO PDF HT48R54A July 27, 2007 ...
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... TO PDF Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. ACC [ PDF HT48R54A July 27, 2007 ...
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... The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr TO PDF Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m] TO PDF HT48R54A July 27, 2007 ...
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... ACC PDF Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m] TO PDF HT48R54A July 27, 2007 ...
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... Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TO PDF HT48R54A July 27, 2007 ...
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... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 TO PDF HT48R54A July 27, 2007 ...
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... If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy- cles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m] 1)=0, ACC ([ PDF HT48R54A July 27, 2007 ...
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... If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other- wise proceed with the next instruction (1 cycle). Skip if [m]. PDF HT48R54A July 27, 2007 ...
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... Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TO PDF HT48R54A July 27, 2007 ...
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... Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO PDF HT48R54A July 27, 2007 ...
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... ACC XOR [m] TO PDF Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x TO PDF HT48R54A July 27, 2007 ...
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... Package Information 44-pin QFP (10´10) Outline Dimensions www.DataSheet4U.com Symbol Rev. 1.00 Dimensions in mm Min. Nom. 13 9.9 13 9.9 0.8 0.3 1.9 0.25 0.73 0.1 0 HT48R54A Max. 13.4 10.1 13.4 10.1 2.2 2.7 0.5 0.93 0.2 7 July 27, 2007 ...
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... QFP (14´14) Outline Dimensions www.DataSheet4U.com Symbol Rev. 1.00 Dimensions in mm Min. Nom. 17.3 13.9 17.3 13.9 1 0.4 2.5 0.1 0.73 0 HT48R54A Max. 17.5 14.1 17.5 14.1 3.1 3.4 1.03 0.2 7 July 27, 2007 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 HT48R54A 40 July 27, 2007 ...