HT48R50A Holtek Semiconductor Inc, HT48R50A Datasheet

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... General Description This device is an 8-bit high performance RISC-like microcontroller designed for multi- ple I/O product applications particularly suitable for use in products such as remote con- Rev. 1.10 HT48R50A-1 8-Bit Microcontroller 4096´15 program memory ROM · · 160´8 data memory RAM · ...

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... Block Diagram Rev. 1.10 HT48R50A-1 2 July 2, 2001 ...

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... Pin Assignment Rev. 1.10 HT48R50A-1 3 July 2, 2001 ...

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... Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resis- tor (determined by 1-bit pull-high option). Timer/Event Counter 1 Schmitt trigger input (without pull-high resistor) Schmitt trigger reset input. Active low Positive power supply 4 HT48R50A-1 July 2, 2001 ...

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... Test Conditions Min. V Conditions DD f =4MHz ¾ 3.3 SYS ¾ f =8MHz 4.5 SYS 3.3V ¾ No load, f =4MHz SYS 5V ¾ 3.3V ¾ No load, f =4MHz SYS 5V ¾ No load, f =8MHz 5V ¾ SYS 5 HT48R50A-1 Ta=25°C Typ. Max. Unit ¾ 5.5 V ¾ 5 July 2, 2001 ...

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... DD 3.3V V =0. =0. 3.3V V =0. =0. ¾ 5V ¾ 10 ¾ 3.3V option 2.7 6 HT48R50A-1 Typ. Max. Unit 5 ¾ mA ¾ ¾ ¾ mA ¾ ¾ 0.3V ¾ ¾ 0.4V ¾ ¾ ¾ ...

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... Without WDT 7.812 ¾ ¾ prescaler 1 ¾ ¾ ¾ ¾ Wake-up from HALT ¾ 1024 ¾ ¾ 1 ¾ 7 HT48R50A-1 Ta=25°C 4000 kHz 8000 kHz 4000 kHz 8000 kHz kHz kHz 4000 kHz 8000 kHz 168 ms 144 ...

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... Certain locations in the program memory are reserved for special usage: · Location 000H This area is reserved for program initializa- tion. After chip reset, the program always be- gins execution at location 000H. Execution flow 8 HT48R50A-1 July 2, 2001 ...

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... PC Program counter S11~S0: Stack register bits @7~@0: PCL bits 9 HT48R50A July 2, 2001 ...

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... Timer/Event Counter 0 control register Table Location * Table location P11~P8: Current program counter bits 10 HT48R50A July 2, 2001 ...

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... RAM mapping Rev. 1.10 HT48R50A-1 (TMR0C;0EH), Timer/Event Counter 1 higher Timer/Event Counter 1 lower order byte regis- ter (TMR1L;10H), Timer/Event Counter 1 con- trol register (TMR1C;11H), program counter lower-order byte register (PCL;06H), memory pointer registers (MP0 ...

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... If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Function Status register 12 HT48R50A-1 July 2, 2001 ...

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... The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts. The internal timer/even counter 1 interrupt is initialized by setting the Timer/Event Counter 1 interrupt request flag (;bit 6 of INTC), caused by a timer 1 overflow. When the interrupt is en- Function INTC register 13 HT48R50A-1 July 2, 2001 ...

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... Crystal oscillator and the internal RC oscillator, which are determined by ROM code option. No matter what oscillator type is se- lected, the signal provides the system clock. The HALT mode stops the system oscillator and ignores an external signal to conserve power. Watchdog Timer 14 HT48R50A-1 July 2, 2001 ...

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... RC+RTC mode. Once the internal WDT oscillator (RC oscillator with a period of 72ms/5V normally) is selected, it Rev. 1.10 HT48R50A-1 is first divided by 256 (8-stage) to get the nomi- nal time-out period of 18.6ms/5V. This time-out period may vary with temperatures, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be real- ized ...

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... If the interrupt is en- Rev. 1.10 HT48R50A-1 abled and the stack is not full, the regular inter- rupt response takes place interrupt request flag is set to "1" before entering the HALT mode, the wake-up function of the re- lated interrupt will be disabled ...

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... When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will enable the SST delay. Reset timing chart Reset circuit Reset configuration Rev. 1.10 HT48R50A-1 The functional unit chip reset status are shown below. PC 000H Interrupt Disable ...

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... PG ---- -111 ---- -111 PGC ---- -111 ---- -111 Note: "*" stands for "warm reset" "u" stands for "unchanged" "x" stands for "unknown" Rev. 1.10 HT48R50A-1 RES Reset RES Reset (Normal Time-out (HALT) Operation) (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu ...

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... SYS RTC / SYS RTC / SYS RTC / /16 SYS RTC / /32 SYS RTC / /64 SYS RTC /128 or f /128 SYS RTC /256 or f /256 SYS RTC TMR0C register Function TMR1C register 19 HT48R50A-1 July 2, 2001 ...

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... Reading TMR1H will latch the contents of TMR1H and TMR1L counters to the destina- tion and the lower-order byte buffer, respec- tively. Reading the TMR1L will read the contents of the lower-order byte buffer. The TMR1C is the Timer/Event Counter 1 control 20 HT48R50A-1 The July 2, 2001 ...

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... But in the other two modes the TON can only be reset by in- structions. The overflow of the Timer/Event Rev. 1.10 HT48R50A-1 Counter 0/1 is one of the wake-up sources. No matter what the operation mode is, writing ET0I/ET1I can disable the corresponding in- terrupt services. ...

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... PB0/PB1 are shown below ² data HT48R50A July 2, 2001 ...

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... The LVR uses the ²OR² function with the ex- ternal RES signal to perform chip reset. The relationship between V shown below. Note the voltage range for proper chip OPR operation at 4MHz system clock. 23 HT48R50A-1 and LVR July 2, 2001 ...

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... PA, PB, PC, PD, PG pull-high enable/disable (By port) 8 BZ/BZ enable/disable 9 LVR enable/disable System oscillator 10 Ext. RC, Ext. crystal, Int. RC+RTC or Int. RC+PG1/PG2 11 Int. RC frequency selection 3.2MHz, 1.6MHz, 800kHz or 400kHz 12 Lock: unlock/lock Rev. 1.10 Low voltage reset Option /RTCOSC/disable TID or RTCOSC SYS /4 or RTCOSC SYS 24 HT48R50A-1 July 2, 2001 ...

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... Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. Rev. 1.10 HT48R50A-1 Crystal or ceramic resonator for multiple I/O applications Note: C1=C2=300pF if f < ...

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... CPLA [m] Complement data memory with result in ACC Increment & Decrement INCA [m] Increment data memory with result in ACC INC [m] Increment data memory DECA [m] Decrement data memory with result in ACC DEC [m] Decrement data memory Rev. 1.10 HT48R50A-1 Instruction Cycle (1) ...

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... Skip if increment data memory is zero with result in ACC SDZA [m] Skip if decrement data memory is zero with result in ACC CALL addr Subroutine call RET Return from subroutine RET A,x Return from subroutine and load immediate data to ACC RETI Return from interrupt Rev. 1.10 HT48R50A-1 Instruction Cycle (1) 1 ...

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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO is set and the PD is cleared. Otherwise the TO and PD flags remain unchanged. Rev. 1.10 HT48R50A-1 Instruction Cycle ( (1) 1 (1) ...

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... Rev. 1. ¾ ¾ Ö Ö Ö Ö ¾ ¾ Ö Ö Ö Ö ¾ ¾ Ö Ö Ö Ö ¾ ¾ Ö Ö Ö Ö 29 HT48R50A-1 July 2, 2001 ...

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... Rev. 1. ¾ ¾ Ö Ö Ö Ö ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 30 HT48R50A-1 July 2, 2001 ...

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... Rev. 1. ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 31 HT48R50A-1 July 2, 2001 ...

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... Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] ¬ [m] Affected flag(s) TC2 TC1 ¾ ¾ Rev. 1. ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 32 HT48R50A-1 July 2, 2001 ...

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... Data in the specified data memory is decremented by 1. Operation [m] ¬ [m]-1 Affected flag(s) TC2 TC1 ¾ ¾ Rev. 1. ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ Ö ¾ ¾ 33 HT48R50A-1 July 2, 2001 ...

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... Rev. 1. ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 34 HT48R50A-1 July 2, 2001 ...

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... ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 35 HT48R50A-1 July 2, 2001 ...

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... Rev. 1. ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 36 HT48R50A-1 July 2, 2001 ...

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... Rev. 1. ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 37 HT48R50A-1 July 2, 2001 ...

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... Affected flag(s) TC2 TC1 ¾ ¾ Rev. 1. ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ ¾ 38 HT48R50A-1 July 2, 2001 ...

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... ACC.7 ¬ ¬ [m].0 Affected flag(s) TC2 TC1 ¾ ¾ Rev. 1. ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö 39 HT48R50A-1 July 2, 2001 ...

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... Operation Skip if ([m]-1)=0, [m] ¬ ([m]-1) Affected flag(s) TC2 TC1 ¾ ¾ Rev. 1. ¾ ¾ Ö Ö Ö Ö ¾ ¾ Ö Ö Ö Ö ¾ ¾ ¾ ¾ ¾ ¾ 40 HT48R50A-1 July 2, 2001 ...

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... Rev. 1. ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 41 HT48R50A-1 July 2, 2001 ...

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... Rev. 1. ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö Ö Ö Ö ¾ ¾ Ö Ö Ö Ö 42 HT48R50A-1 July 2, 2001 ...

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... Rev. 1. ¾ ¾ Ö Ö Ö Ö ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 43 HT48R50A-1 July 2, 2001 ...

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... Rev. 1. ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 44 HT48R50A-1 July 2, 2001 ...

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... ACC ¬ ACC "XOR" x Affected flag(s) TC2 TC1 ¾ ¾ Rev. 1. ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 45 HT48R50A-1 July 2, 2001 ...

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... Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.10 HT48R50A-1 46 July 2, 2001 ...