HT48R10A Holtek Semiconductor Inc, HT48R10A Datasheet

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... The device is an 8-bit high performance RISC-like microcontroller designed for multi- ple I/O product applications. The device is par- ticularly suitable for use in products such as Rev. 1.20 HT48R10A-1 8-Bit Microcontroller · Buzzer driving pair and PFD supported · HALT function and wake-up feature reduce power consumption ...

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... Block Diagram Pin Assignment Rev. 1.20 HT48R10A-1 2 July 2, 2001 ...

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... Otherwise the PC3 and PC4 are used as internal regis- ters (pull-high resistors are always disabled). Note: ²*² The pull-high resistors of each I/O port (PA, PB, PC) are controlled by 1-bit ROM code options. or Schmitt trigger option of port A is controlled by 1-bit ROM code option. Rev. 1.20 HT48R10A-1 Description 3 July 2, 2001 ...

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... No load, system HALT 5V ¾ 3.3V ¾ No load, system HALT 5V ¾ 0 ¾ ¾ ¾ ¾ 0.7 0 ¾ ¾ 0.9V ¾ ¾ DD 3.3V V =0. =0. HT48R10A-1 Ta=25°C Typ. Max. Unit ¾ 5.5 V ¾ 5 ¾ mA ¾ ¾ ...

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... Without WDT 11 prescaler 5V 9 Without WDT ¾ ¾ prescaler Without WDT ¾ ¾ prescaler ¾ ¾ 1 Wake-up from ¾ ¾ HALT ¾ ¾ HT48R10A-1 Typ. Max. Unit -4 ¾ mA -10 ¾ 3.0 3.3 V Ta=25°C Typ. Max. Unit 4000 kHz ¾ ...

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... Location 004H This area is reserved for the external inter- rupt service program. If the INT input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004H. Execution flow 6 HT48R10A-1 July 2, 2001 ...

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... PC Program counter S9~S0: Stack register bits @7~@0: PCL bits 7 HT48R10A July 2, 2001 ...

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... Any writing operation to MP will only transfer the lower 7-bit data to MP. Table Location * Table location P9, P8: Current program counter bits 8 HT48R10A July 2, 2001 ...

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... The data movement between two data memory locations must pass through the accumulator. Rev. 1.20 HT48R10A-1 Arithmetic and logic unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following func- tions: ...

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... To return from the interrupt subroutine, "RET" or "RETI" may be invoked. RETI will set the EMI bit to en- able an interrupt service, but RET will not. Function Status register 10 HT48R10A-1 July 2, 2001 ...

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... All of them are designed for system clocks, namely the external RC oscillator, the external Crystal oscillator and the internal RC oscillator, which are determined by the ROM code option. No matter what oscillator type is selected, the signal provides the system clock. Function INTC register 11 HT48R10A-1 July 2, 2001 ...

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... If the device operates in a noisy environment, us- ing the on-chip RC oscillator (WDT OSC) or 32kHz crystal oscillator (RTC OSC) is strongly recommended, since the HALT will stop the sys- tem clock. Watchdog Timer 12 HT48R10A-1 July 2, 2001 ...

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... WDT oscillator). · All of the I/O ports maintain their original sta- tus. Rev. 1.20 HT48R10A-1 · The PD flag is set and the TO flag is cleared. The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port WDT overflow. ...

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... HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will enable the SST delay. Reset timing chart Rev. 1.20 HT48R10A-1 Reset circuit Reset configuration The functional unit chip reset status are shown below. PC ...

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... PC ---1 1111 ---1 1111 PCC ---1 1111 ---1 1111 Note: "*" means "warm reset" "u" means "unchanged" "x" means "unknown" Rev. 1.20 HT48R10A-1 RES Reset RES Reset (Normal Time-out (HALT) Operation) (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu 00-0 1000 ...

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... SYS RTC / SYS RTC / SYS RTC / /16 SYS RTC / /32 SYS RTC / /64 SYS RTC /128 or f /128 SYS RTC /256 or f /256 SYS RTC TMRC register Timer/Event Counter 16 HT48R10A-1 July 2, 2001 ...

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... ETI can disable the interrupt service. In the case of timer/event counter OFF condi- Rev. 1.20 HT48R10A-1 tion, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. But if the timer/event counter is turned on, data written to it will only be kept in the timer/event counter preload reg- ister ...

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... PB0 Pad Status PB1 Pad Status Note: ²I² input, ²O² output, ²D, D ²B² buzzer option BZ, ²x² don't care ²C² CMOS output 18 HT48R10A ...

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... The LVR uses the ²OR² function with the ex- ternal RES signal to perform chip reset. The relationship between V shown below. Note the voltage range for proper chip OPR operation at 4MHz system clock. Low voltage reset 19 HT48R10A-1 and LVR July 2, 2001 ...

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... PA wake- CMOS/SCHMITT input 6 PA pull-high enable/disable 7 PB pull-high enable/disable 8 PC pull-high enable/disable 9 BZ/BZ enable/disable 10 LVR enable/disable System oscillator 11 Ext.RC, Ext.crystal, Int.RC+RTC or Int.RC+PC3/PC4 12 Int.RC frequency selection 3.2MHz, 1.6MHz, 800kHz or 400kHz Rev. 1.20 Option /RTCOSC/disable TID or RTCOSC SYS 20 HT48R10A-1 July 2, 2001 ...

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... Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. Rev. 1.20 HT48R10A-1 Crystal or ceramic resonator for multiple I/O applications Note: C1=C2=300pF if f < ...

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... CPLA [m] Complement data memory with result in ACC Increment & Decrement INCA [m] Increment data memory with result in ACC INC [m] Increment data memory DECA [m] Decrement data memory with result in ACC DEC [m] Decrement data memory Rev. 1.20 HT48R10A-1 Instruction Cycle (1) ...

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... Skip if increment data memory is zero with result in ACC SDZA [m] Skip if decrement data memory is zero with result in ACC CALL addr Subroutine call RET Return from subroutine RET A,x Return from subroutine and load immediate data to ACC RETI Return from interrupt Rev. 1.20 HT48R10A-1 Instruction Cycle (1) 1 ...

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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO is set and the PD is cleared. Otherwise the TO and PD flags remain unchanged. Rev. 1.20 HT48R10A-1 Instruction Cycle ( (1) 1 (1) ...

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... Rev. 1. ¾ ¾ Ö Ö Ö Ö ¾ ¾ Ö Ö Ö Ö ¾ ¾ Ö Ö Ö Ö ¾ ¾ Ö Ö Ö Ö 25 HT48R10A-1 July 2, 2001 ...

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... Rev. 1. ¾ ¾ Ö Ö Ö Ö ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 26 HT48R10A-1 July 2, 2001 ...

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... Rev. 1. ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 27 HT48R10A-1 July 2, 2001 ...

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... Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] ¬ [m] Affected flag(s) TC2 TC1 ¾ ¾ Rev. 1. ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 28 HT48R10A-1 July 2, 2001 ...

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... Data in the specified data memory is decremented by 1 Operation [m] ¬ [m]-1 Affected flag(s) TC2 TC1 ¾ ¾ Rev. 1. ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ Ö ¾ ¾ 29 HT48R10A-1 July 2, 2001 ...

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... Rev. 1. ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 30 HT48R10A-1 July 2, 2001 ...

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... ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 31 HT48R10A-1 July 2, 2001 ...

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... Rev. 1. ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 32 HT48R10A-1 July 2, 2001 ...

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... Rev. 1. ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 33 HT48R10A-1 July 2, 2001 ...

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... Affected flag(s) TC2 TC1 ¾ ¾ Rev. 1. ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ ¾ 34 HT48R10A-1 July 2, 2001 ...

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... ACC.7 ¬ ¬ [m].0 Affected flag(s) TC2 TC1 ¾ ¾ Rev. 1. ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö 35 HT48R10A-1 July 2, 2001 ...

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... Operation Skip if ([m]-1)=0, [m] ¬ ([m]-1) Affected flag(s) TC2 TC1 ¾ ¾ Rev. 1. ¾ ¾ Ö Ö Ö Ö ¾ ¾ Ö Ö Ö Ö ¾ ¾ ¾ ¾ ¾ ¾ 36 HT48R10A-1 July 2, 2001 ...

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... Rev. 1. ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 37 HT48R10A-1 July 2, 2001 ...

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... Rev. 1. ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö Ö Ö Ö ¾ ¾ Ö Ö Ö Ö 38 HT48R10A-1 July 2, 2001 ...

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... Rev. 1. ¾ ¾ Ö Ö Ö Ö ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 39 HT48R10A-1 July 2, 2001 ...

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... Rev. 1. ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 40 HT48R10A-1 July 2, 2001 ...

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... ACC ¬ ACC "XOR" x Affected flag(s) TC2 TC1 ¾ ¾ Rev. 1. ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 41 HT48R10A-1 July 2, 2001 ...

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... Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.20 HT48R10A-1 42 July 2, 2001 ...