HT48CA0-2 Holtek Semiconductor, HT48CA0-2 Datasheet
HT48CA0-2
Available stocks
Related parts for HT48CA0-2
HT48CA0-2 Summary of contents
Page 1
... General Description The HT48RA0-2/HT48CA0-2 are 8-bit high perfor- mance, RISC architecture microcontroller devices spe- cifically designed for multiple I/O control product applications. The mask version HT48CA0-2 is fully pin and functionally compatible with the OTP version HT48RA0-2 device. Block Diagram Rev. 1.50 ...
Page 2
... In the case of RC operation, OSC2 the output terminal for 1/4 system clock (NMOS open drain output). I Schmitt trigger reset input. Active low. 0. +4.0V Storage Temperature ............................ 125 0. +0.3V Operating Temperature........................... HT48RA0-2/HT48CA0-2 Description July 23, 2004 ...
Page 3
... Low Voltage Width to Reset LVR Note: t =1/f SYS SYS Functional Description Execution Flow The HT48RA0-2/HT48CA0-2 system clock can be de- rived from a crystal/ceramic resonator oscillator in- ternally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Rev. 1.50 Test Conditions Parameter V ...
Page 4
... Program Counter S9~S0: Stack register bits @7~@0: PCL bits Table Location * Table Location @7~@0: Table pointer bits 4 HT48RA0-2/HT48CA0-2 Program Memory * ...
Page 5
... SET [m].i and CLR [m].i instructions, respectively. They are also indirectly accessible through memory pointer register (MP;01H). Rev. 1.50 HT48RA0-2/HT48CA0-2 RAM Mapping Indirect Addressing Register Location 00H is an indirect addressing register that is not physically implemented. Any read/write operation of [00H] accesses data memory pointed (01H) ...
Page 6
... PDF is cleared when either a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction cleared by a system power-up or executing the CLR WDT or HALT instruction set by a WDT time-out. Unused bit, read as 0 Status Register 6 HT48RA0-2/HT48CA0-2 System Oscillator , temperature and the chip DD July 23, 2004 ...
Page 7
... Once a wake-up event(s) occurs, it takes 1024 t CLR WDT (system clock period) to resume normal operation. In other words, a dummy cycle period will be inserted after the wake-up. To minimize power consumption, all I/O pins should be carefully managed before entering the HALT status. Watchdog Timer 7 HT48RA0-2/HT48CA0-2 SYS July 23, 2004 ...
Page 8
... HT48RA0-2/HT48CA0-2 Reset Timing Chart Reset Circuit Reset Configuration RES Reset WDT Time-out (HALT) (HALT)* 000H 000H 000H -uuu uuuu -uuu uuuu uuuu uuuu ...
Page 9
... Note: The bit 6 and Bit 7 the PB register (14H) are un- used in the HT48RA0-2/HT48CA0-2, any read from that will return the value 0 . User Should be very careful in transferring the program from the HT48RA0A or HT48RA0-1/HT48CA0-1 device to the HT48RA0-2/ HT48CA0-2 device ...
Page 10
... LVR will ignore it and do not perform a reset function. Rev. 1.50 PA, PB Input/Output Lines PB Input Lines The LVR uses the OR function with the external RES signal to perform chip reset. The relationship between V ) has to remain in their LVR 10 HT48RA0-2/HT48CA0-2 and V is shown below. DD LVR July 23, 2004 ...
Page 11
... Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters the reset mode. Code Option The following table shows eight kinds of code option in the HT48RA0-2/HT48CA0-2. All the code options must be de- fined to ensure proper system functioning. No. ...
Page 12
... The following table shows the C value according to different crystal values. (For reference only) 4MHz Crystal 4MHz Resonator 3.58MHz Crystal 3.58MHz Resonator 2MHz Crystal & Resonator 1MHz Crystal 480kHz Resonator 455kHz Resonator 429kHz Resonator Rev. 1.50 Crystal or Resonator 0pF 10pF 0pF 25pF 25pF 35pF 300pF 300pF 300pF 12 HT48RA0-2/HT48CA0-2 C July 23, 2004 ...
Page 13
... Rotate data memory left through carry with result in ACC Rotate data memory left through carry Move data memory to ACC Move ACC to data memory Move immediate data to ACC Clear bit of data memory Set bit of data memory 13 HT48RA0-2/HT48CA0-2 Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) ...
Page 14
... No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode (2) 14 HT48RA0-2/HT48CA0-2 Instruction Flag Cycle Affected 2 None (2) 1 None (2) ...
Page 15
... The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x TO PDF Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m] TO PDF HT48RA0-2/HT48CA0 July 23, 2004 ...
Page 16
... The indicated address is then loaded. Program execution continues with the instruction at this address. Stack PC+1 PC addr TO PDF Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H TO PDF HT48RA0-2/HT48CA0 July 23, 2004 ...
Page 17
... WDT 00H* PDF and PDF Complement data memory Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] TO PDF HT48RA0-2/HT48CA0 July 23, 2004 ...
Page 18
... PDF Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. ACC [ PDF HT48RA0-2/HT48CA0 July 23, 2004 ...
Page 19
... The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. PC addr TO PDF Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m] TO PDF HT48RA0-2/HT48CA0 July 23, 2004 ...
Page 20
... PDF Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m] TO PDF HT48RA0-2/HT48CA0 July 23, 2004 ...
Page 21
... The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re- places the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m]. [m].7 TO PDF HT48RA0-2/HT48CA0 July 23, 2004 ...
Page 22
... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 TO PDF HT48RA0-2/HT48CA0 July 23, 2004 ...
Page 23
... If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy- cles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m] 1)=0, ACC ([ PDF HT48RA0-2/HT48CA0 July 23, 2004 ...
Page 24
... If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other- wise proceed with the next instruction (1 cycle). Skip if [m]. PDF HT48RA0-2/HT48CA0 July 23, 2004 ...
Page 25
... Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TO PDF HT48RA0-2/HT48CA0 July 23, 2004 ...
Page 26
... Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH code (high byte) TO PDF HT48RA0-2/HT48CA0 July 23, 2004 ...
Page 27
... ACC XOR [m] TO PDF Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x TO PDF HT48RA0-2/HT48CA0 July 23, 2004 ...
Page 28
... Package Information 20-pin SOP (300mil) Outline Dimensions www.DataSheet4U.com Symbol Rev. 1.50 HT48RA0-2/HT48CA0-2 Dimensions in mil Min. Nom. 394 290 14 490 Max. 419 300 20 510 104 July 23, 2004 ...
Page 29
... SSOP (150mil) Outline Dimensions www.DataSheet4U.com Symbol Rev. 1.50 HT48RA0-2/HT48CA0-2 Dimensions in mil Min. Nom. 228 150 8 335 Max. 244 158 12 347 July 23, 2004 ...
Page 30
... Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness 30 HT48RA0-2/HT48CA0-2 Dimensions in mm 330 1.0 62 1.5 13.0+0.5 0.2 2.0 0.5 24.8+0.3 0.2 30.2 0.2 Dimensions in mm 330 1.0 62 1.5 13.0+0.5 ...
Page 31
... Cover Tape Width Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width 31 HT48RA0-2/HT48CA0-2 Dimensions in mm 24.0+0.3 0.1 12.0 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4.0 0.1 2.0 0.1 10.8 0.1 13.3 0.1 3.2 0.1 0.3 0.05 21.3 Dimensions ...
Page 32
... Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.50 HT48RA0-2/HT48CA0-2 32 July 23, 2004 ...